Datasheet

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
32 Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
This figure shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
It assumes the DC levels of the clock driver are compatible with the device’s SerDes reference clock
input’s DC requirement.
Figure 23. Single-Ended Connection (Reference Only)
10.2.4 AC Requirements for SerDes Reference Clocks
The clock driver selected should provide a high quality reference clock with low phase noise and
cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise
occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50  to match the
transmission line and reduce reflections which are a source of noise to the system.
This table describes some AC parameters for PCI Express protocol.
Table 32. SerDes Reference Clock AC Parameters
At recommended operating conditions with XCOREVDD= 1.0V ± 5%
Parameter Symbol Min Max Unit Notes
Rising Edge Rate Rise Edge Rate 1.0 4.0 V/ns 2, 3
Falling Edge Rate Fall Edge Rate 1.0 4.0 V/ns 2, 3
Differential Input High Voltage V
IH
+200 — mV 2
Differential Input Low Voltage V
IL
— –200 mV 2
50 
50 
SD_REF_CLK
SD_REF_CLK
100 differential PWB trace
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
Single-Ended
CLK Driver Chip
MPC8308
33 
Total 50 Assume clock driver’s
output impedance is about 16 
50 