Datasheet

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3

Freescale Semiconductor 29

High-Speed Serial Interfaces (HSSI)

Figure 17. Differential Reference Clock Input DC Requirements (External DC-Coupled)

Figure 18. Differential Reference Clock Input DC Requirements (External AC-Coupled)

Figure 19. Single-Ended Reference Clock Input DC Requirements

10.2.3 Interfacing with Other Differential Signaling Levels

With on-chip termination to XCOREVSS, the differential reference clocks inputs are high-speed current

steering logic (HCSL) compatible and DC coupled.

Many other low voltage differential type outputs like low-voltage differential signaling (LVDS) can be

used but may need to be AC-coupled due to the limited common mode input range allowed (100–400 mV)

for DC-coupled connection.

LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock

driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to

AC-coupling.

SD_REF_CLK

Vmax < 80 0mV

Vmin > 0V

100 mV <

Vcm < 400 mV

200 mV < Input Amplitude or Differential Peak < 800mV

SD_REF_CLK

Vcm

200mV < Input Amplitude or Differential Peak < 800mV

Vmax < Vcm + 400 mV

Vmin >

Vcm – 400 mV

SD_REF_CLK

400 mV < SD_REF_CLK Input Amplitude < 800 mV