Datasheet

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
20 Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
This figure shows the RGMII AC timing and multiplexing diagrams.
Figure 11. RGMII AC Timing and Multiplexing Diagrams
8.3 Ethernet Management Interface Electrical Characteristics
The electrical characteristics specified here apply to MII management interface signals MDIO
(management data input/output) and MDC (management data clock). The electrical characteristics for MII
GTX_CLK125 reference clock period t
G12
6
—8.0—ns
GTX_CLK125 reference clock duty cycle t
G125H
/t
G125
47 — 53 %
Notes:
1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII timing.
For example, the subscript of t
RGT
represents the RGMII receive (RX) clock. Note also that the notation for rise (R) and fall
(F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is skew (SK)
followed by the clock that is being skewed (RGT).
2. This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns is
added to the associated clock signal.
3. For 10 and 100 Mbps, t
RGT
scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long
as the minimum duty cycle is not violated and stretching occurs for no more than three t
RGT
of the lowest speed transitioned
between.
5. Duty cycle reference is 0.5*LV
DD
6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
Table 25. RGMII AC Timing Specifications (continued)
At recommended operating conditions with LV
DD
of 2.5 V ± 5%.
GTX_CLK
t
RGT
t
RGTH
t
SKRGT
TX_CTL
TXD[8:5]
TXD[7:4]
TXD[9]
TXERR
TXD[4]
TXEN
TXD[3:0]
(At Transmitter)
TXD[8:5][3:0]
TXD[7:4][3:0]
TX_CLK
(At PHY)
RX_CTL
RXD[8:5]
RXD[7:4]
RXD[9]
RXERR
RXD[4]
RXDV
RXD[3:0]
RXD[8:5][3:0]
RXD[7:4][3:0]
RX_CLK
(At PHY)
t
SKRGT
t
SKRGT
t
SKRGT