Datasheet

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
2 Freescale Semiconductor
Overview
1 Overview
This figure shows the major functional units within the MPC8308. The e300 core in the MPC8308, with
its 16 Kbytes of instruction and 16 Kbytes of data cache, implements the Power Architecture user
instruction set architecture and provides hardware and software debugging support. In addition, the
MPC8308 offers a PCI Express controller, two three-speed 10, 100, 1000 Mbps Ethernet controllers
(eTSEC), a DDR2 SDRAM memory controller, a SerDes block, an enhanced local bus controller (eLBC),
an integrated programmable interrupt controller (IPIC), a general purpose DMA controller, two I
2
C
controllers, dual UART (DUART), GPIOs, USB, general purpose timers, and an SPI controller. The high
level of integration in the MPC8308 helps simplify board design and offers significant bandwidth and
performance.
This figure shows a block diagram of the device.
Figure 1. MPC8308 Block Diagram
2 Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8308. The device is currently targeted to these specifications. Some of these specifications are
independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer
design specifications.
2.1 Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
eTSEC1
DUART
Interrupt
I2C
Timers
GPIO, SPI
Enhanced
DDR2
Controller
Controller
Local Bus
PCI
Express
x1
DMA
RGMII,MII
16-Kbyte
D-Cache
16-Kbyte
I-Cache
e300c3 Core with
Power Management
FPU
Enhanced
Secure
Digital Host
Controller
USB 2.0 HS
Host/Device/OTG
eTSEC2
RGMII,MII
ULPI