Datasheet

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Freescale Semiconductor 19
Ethernet: Three-Speed Ethernet, MII Management
This figure shows the MII receive AC timing diagram.
Figure 9. MII Receive AC Timing Diagram RMII AC Timing Specifications
This figure provides the AC test load.
Figure 10. AC Test Load
8.2.2 RGMII AC Timing Specifications
This table presents the RGMII AC timing specifications.
Table 25. RGMII AC Timing Specifications
At recommended operating conditions with LV
DD
of 2.5 V ± 5%.
Parameter/Condition Symbol
1
Min Typ Max Unit
Data to clock output skew (at transmitter) t
SKRGT
–0.6 — 0.6 ns
Data to clock input skew (at receiver)
2
t
SKRGT
1.0 — 2.6 ns
Clock cycle duration
3
t
RGT
7.2 8.0 8.8 ns
Duty cycle for 1000Base-T
4, 5
t
RGTH
/t
RGT
45 50 55 %
Duty cycle for 10BASE-T and 100BASE-TX
3, 5
t
RGTH
/t
RGT
40 50 60 %
Rise time (20%–80%) t
RGTR
— — 0.75 ns
Fall time (20%–80%) t
RGTF
— — 0.75 ns
RX_CLK
RXD[3:0]
t
MRDXKH
t
MRX
t
MRXH
t
MRXR
t
MRXF
RX_DV
RX_ER
t
MRDVKH
Valid Data
Output
Z
0
= 50 
NV
DD/
2
R
L
= 50 
or
LV
DD
/2