Datasheet

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
14 Freescale Semiconductor
DDR2 SDRAM
This figure shows the DDR2 SDRAM output timing for the MCK to MDQS skew measurement
(tDDKHMH).
Figure 5. Timing Diagram for t
DDKHMH
This figure shows the DDR2 SDRAM output timing diagram.
Figure 6. DDR2 SDRAM Output Timing Diagram
MDQS
MCK[n]
MCK[n]
t
MCK
t
DDKHMHmax) = 0.6 ns
t
DDKHMH(min) = –0.6 ns
MDQS
ADDR/CMD
t
DDKHAS
,t
DDKHCS
t
DDKHMH
t
DDKLDS
t
DDKHDS
MDQ[x]/
MDQS[n]
MCK
[n]
MCK[n]
t
MCK
t
DDKLDX
t
DDKHDX
D1D0
t
DDKHAX
,t
DDKHCX
Write A0 NOOP
t
DDKHME
t
DDKHMP
MECC[x]