Datasheet

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
12 Freescale Semiconductor
DDR2 SDRAM
This figure illustrates the DDR2 input timing diagram showing the t
DISKEW
timing parameter.
Figure 4. Timing Diagram for t
DISKEW
6.2.2 DDR2 SDRAM Output AC Timing Specifications
Table 18. DDR2 SDRAM Output AC Timing Specifications
Parameter Symbol
1
Min Max Unit Notes
MCK[n] cycle time, MCK[n]/MCK
[n] crossing t
MCK
7.5 10 ns 2
ADDR/CMD output setup with respect to MCK t
DDKHAS
—ns3
266 MHz 2.9
ADDR/CMD output hold with respect to MCK t
DDKHAX
—ns3
266 MHz 2.33
MCS
[n] output setup with respect to MCK t
DDKHCS
—ns3
266 MHz 2.5
MCS
[n] output hold with respect to MCK t
DDKHCX
—ns3
266 MHz 3.15
MCK to MDQS Skew t
DDKHMH
–0.6 0.6 ns 4
MCK[n]
MCK[n]
t
MCK
MDQ[x]/
MDQS[n]
t
DISKEW
D1D0
t
DISKEW
MECC[x]