Datasheet

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Freescale Semiconductor 11
DDR2 SDRAM
This table provides the current draw characteristics for MV
REF
.
6.2 DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR2 SDRAM interface.
6.2.1 DDR2 SDRAM Input AC Timing Specifications
This table provides input AC timing specifications for the DDR2 SDRAM when GV
DD
(typ)=1.8 V.
This table provides input AC timing specifications for the DDR2 SDRAM interface.
Table 15. Current Draw Characteristics for MV
REF
Parameter / Condition Symbol Min Max Unit Note
Current draw for MV
REF
I
MVREF
— 500 A1
Note:
1. The voltage regulator for MV
REF
must be able to supply up to 500 A current.
Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8 V Interface
At recommended operating conditions with GV
DD
of 1.8 ± 100 mV
Parameter Symbol Min Max Unit Notes
AC input low voltage V
IL
—MV
REF
– 0.45 V —
AC input high voltage V
IH
MV
REF
+ 0.45 — V —
Table 17. DDR2 SDRAM Input AC Timing Specifications
At recommended operating conditions. with GV
DD
of 1.8± 100 mV
Parameter Symbol Min Max Unit Notes
Controller skew for MDQS—MDQ/MECC
266 MHz
t
CISKEW
–875 875 ps 1, 2,3
Notes:
1. t
CISKEW
represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is
captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The
amount of skew that can be tolerated from MDQS to a corresponding MDQ or MECC signal is called t
DISKEW
. This can
be determined by the following equation: t
DISKEW
= +/–(T/4 – abs(t
CISKEW
)) where T is the clock period and abs(t
CISKEW
) is
the absolute value of t
CISKEW
.
3. Memory controller ODT value of 150  is recommended