Freescale Semiconductor Document Number: MPC8308EC Rev. 3, 10/2011 MPC8308 PowerQUICC II Pro Processor Hardware Specification This document provides an overview of the MPC8308 features and its hardware specifications, including a block diagram showing the major functional components. The MPC8308 is a cost-effective, low-power, highly integrated host processor.
Overview 1 Overview This figure shows the major functional units within the MPC8308. The e300 core in the MPC8308, with its 16 Kbytes of instruction and 16 Kbytes of data cache, implements the Power Architecture user instruction set architecture and provides hardware and software debugging support.
Electrical Characteristics 2.1.1 Absolute Maximum Ratings This table lists the absolute maximum ratings. Table 1. Absolute Maximum Ratings1 Characteristic Symbol Max Value Unit Notes Core supply voltage VDD –0.3 to 1.26 V — PLL supply voltage AVDD1, AVDD2 –0.3 to 1.26 V — DDR2 DRAM I/O voltage GVDD –0.3 to 1.9 V — Local bus, DUART, system control and power management, eSDHC, I2C, USB, Interrupt, Ethernet management, SPI, Miscellaneous and JTAG I/O voltage NVDD –0.3 to 3.
Electrical Characteristics Table 2. Recommended Operating Conditions Symbol Recommended Value1 Unit SerDes internal digital power XCOREVDD 1.0 V ± 50 mV V SerDes internal digital power XCOREVSS 0.0 V SerDes I/O digital power XPADVDD 1.0 V ± 50 mV V SerDes analog power for PLL SDAVDD 1.0 V ± 50 mV V SerDes analog power for PLL SDAVSS 0 V SerDes I/O digital power XPADVSS 0 V VDD 1.0 V ± 50 mV V Analog supply for e300 core APLL2 AVDD1 1.
Electrical Characteristics This figure shows the undershoot and overshoot voltages at the interfaces of the device. G/L/NVDD + 20% G/L/NVDD + 5% G/L/NVDD VIH VSS VSS – 0.3 V VIL VSS – 0.7 V Not to Exceed 10% of tinterface1 Note: 1. tinterface refers to the clock period associated with the bus clock interface. Figure 2. Overshoot/Undershoot Voltage for GVDD/NVDD/LVDD 2.1.3 Output Driver Characteristics This table provides information on the characteristics of the output driver strengths. Table 3.
Power Characteristics The I/O power supply ramp-up slew rate should be slower than 4V/100 s, this requirement is for ESD circuit. Note that there is no specific power down sequence requirement for the device. I/O voltage supplies (GVDD, LVDD, and NVDD) do not have any ordering requirements with respect to one another. I/O Voltage (GVDD, LVDD, and NVDD) V Core Voltage (VDD) 0.7 V 90% t 0 PORESET >= 32 tSYS_CLK_IN Figure 3.
Clock Input Timing This table describes a typical scenario where blocks with the stated percentage of utilization and impedances consume the amount of power described. 1 Table 5. MPC8308 Typical I/O Power Dissipation GVDD (1.8 V) NVDD (3.3 V) LVDD/ (3.3 V) LVDD (2.5 V) Unit Comments 250 MHz 32 bits+ECC 266 MHz 32 bits+ECC 0.302 — — — W — 62.5 MHz 66 MHZ — 0.038 0.040 — — W — MII, 25 MHz — — 0.008 — W 2 controllers RGMII, 125 MHz — — 0.078 0.
RESET Initialization Table 8. SYS_CLK_IN AC Timing Specifications Parameter/ Symbol Min Typ Max Unit Notes SYS_CLK_IN frequency fSYS_CLK_IN 24 — 66.67 MHz 1, 6 SYS_CLK_IN period tSYS_CLK_IN 15 — 41.67 ns — tKH, tKL 0.6 1.2 ns 2 tKHK/tSYS_CLK_IN 40 — 60 % 3 — — — ±150 ps 4, 5 SYS_CLK_IN rise and fall time SYS_CLK_IN duty cycle SYS_CLK_IN jitter Notes: 1. Caution: The system and core must not exceed their respective maximum or minimum operating frequencies. 2.
RESET Initialization 5.2 RESET AC Electrical Characteristics This table provides the reset initialization AC timing specifications. Table 11.
DDR2 SDRAM 6 DDR2 SDRAM This section describes the DC and AC electrical specifications for the DDR2 SDRAM interface. Note that DDR2 SDRAM is GVDD(typ) = 1.8 V. 6.1 DDR2 SDRAM DC Electrical Characteristics This table provides the recommended operating conditions for the DDR2 SDRAM component(s) when GVDD(typ) = 1.8 V. Table 13. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V Parameter/Condition Symbol Min Max Unit Note I/O supply voltage GVDD 1.7 1.
DDR2 SDRAM This table provides the current draw characteristics for MVREF. Table 15. Current Draw Characteristics for MVREF Parameter / Condition Current draw for MVREF Symbol Min Max Unit Note IMVREF — 500 A 1 Note: 1. The voltage regulator for MVREF must be able to supply up to 500 A current. 6.2 DDR2 SDRAM AC Electrical Characteristics This section provides the AC electrical characteristics for the DDR2 SDRAM interface. 6.2.
DDR2 SDRAM This figure illustrates the DDR2 input timing diagram showing the tDISKEW timing parameter. MCK[n] MCK[n] tMCK MDQS[n] MDQ[x]/ MECC[x] D0 D1 tDISKEW tDISKEW Figure 4. Timing Diagram for tDISKEW 6.2.2 DDR2 SDRAM Output AC Timing Specifications Table 18. DDR2 SDRAM Output AC Timing Specifications Parameter MCK[n] cycle time, MCK[n]/MCK[n] crossing ADDR/CMD output setup with respect to MCK Symbol 1 Min Max Unit Notes tMCK 7.5 10 ns 2 — ns 3 — ns 3 — ns 3 — ns 3 0.
DDR2 SDRAM Table 18. DDR2 SDRAM Output AC Timing Specifications (continued) Symbol 1 Parameter MDQ//MDM/MECC output setup with respect to MDQS tDDKHDS, tDDKLDS 266 MHz MDQ//MDM/MECC output hold with respect to MDQS Min Max Unit Notes — ps 5 — ps 5 900 tDDKHDX, tDDKLDX 266 MHz 1100 MDQS preamble start tDDKHMP 0.75 x tMCK — ns 6 MDQS epilogue end tDDKHME 0.4 x tMCK 0.6 x tMCK ns 6 Notes: 1.
DDR2 SDRAM This figure shows the DDR2 SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH). MCK[n] MCK[n] tMCK tDDKHMHmax) = 0.6 ns MDQS tDDKHMH(min) = –0.6 ns MDQS Figure 5. Timing Diagram for tDDKHMH This figure shows the DDR2 SDRAM output timing diagram. MCK[n] MCK[n] tMCK tDDKHAS,tDDKHCS tDDKHAX,tDDKHCX ADDR/CMD Write A0 NOOP tDDKHMP tDDKHMH MDQS[n] tDDKHME tDDKHDS tDDKLDS MDQ[x]/ MECC[x] D0 D1 tDDKLDX tDDKHDX Figure 6.
DUART This figure provides the AC test load for the DDR2 bus. Z0 = 50 Output GVDD/2 RL = 50 Figure 7. DDR2 AC Test Load 7 DUART This section describes the DC and AC electrical specifications for the DUART interface. 7.1 DUART DC Electrical Characteristics This table provides the DC electrical characteristics for the DUART interface. Table 19. DUART DC Electrical Characteristics Parameter Symbol Min Max Unit High-level input voltage VIH 2.1 NVDD + 0.
Ethernet: Three-Speed Ethernet, MII Management 8.1 Enhanced Three-Speed Ethernet Controller (eTSEC) (10/100/1000 Mbps)—MII/RGMII Electrical Characteristics The electrical characteristics specified here apply to all the media independent interface (MII) and reduced gigabit media independent interface (RGMII), signals except management data input/output (MDIO) and management data clock (MDC). The RGMII interface is defined for 2.5 V, while the MII interface can be operated at 3.3 V.
Ethernet: Three-Speed Ethernet, MII Management Table 22. RGMII DC Electrical Characteristics Parameters Symbol Conditions Min Max Unit Supply voltage 2.5 V LVDD — 2.37 2.63 V Output high voltage VOH IOH = –1.0 mA LVDD = Min 2.00 LVDD + 0.3 V Output low voltage VOL IOL = 1.0 mA LVDD= Min VSS– 0.3 0.40 V Input high voltage VIH — LVDD = Min 1.7 LVDD + 0.3 V Input low voltage VIL — LVDD = Min –0.3 0.
Ethernet: Three-Speed Ethernet, MII Management This figure shows the MII transmit AC timing diagram. tMTXR tMTX TX_CLK tMTXH tMTXF TXD[3:0] TX_EN TX_ER tMTKHDX Figure 8. MII Transmit AC Timing Diagram 8.2.1.2 MII Receive AC Timing Specifications This table provides the MII receive AC timing specifications. Table 24. MII Receive AC Timing Specifications At recommended operating conditions with LVDD /NVDD of 3.3 V ± 0.3V.
Ethernet: Three-Speed Ethernet, MII Management This figure shows the MII receive AC timing diagram. tMRXR tMRX RX_CLK tMRXF tMRXH RXD[3:0] RX_DV RX_ER Valid Data tMRDVKH tMRDXKH Figure 9. MII Receive AC Timing Diagram RMII AC Timing Specifications This figure provides the AC test load. Z0 = 50 Output RL = 50 NVDD/2 or LVDD/2 Figure 10. AC Test Load 8.2.2 RGMII AC Timing Specifications This table presents the RGMII AC timing specifications. Table 25.
Ethernet: Three-Speed Ethernet, MII Management Table 25. RGMII AC Timing Specifications (continued) At recommended operating conditions with LVDD of 2.5 V ± 5%. tG12 6 — 8.0 — ns tG125H/tG125 47 — 53 % GTX_CLK125 reference clock period GTX_CLK125 reference clock duty cycle Notes: 1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII timing. For example, the subscript of tRGT represents the RGMII receive (RX) clock.
Ethernet: Three-Speed Ethernet, MII Management and RGMII are specified in Section 8.1, “Enhanced Three-Speed Ethernet Controller (eTSEC) (10/100/1000 Mbps)—MII/RGMII Electrical Characteristics.” 8.3.1 MII Management DC Electrical Characteristics The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. This table provides the DC electrical characteristics for MDIO and MDC. Table 26. MII Management DC Electrical Characteristics When Powered at 3.
Ethernet: Three-Speed Ethernet, MII Management Table 27. MII Management AC Timing Specifications (continued) At recommended operating conditions with LVDDA/LVDDB is 3.3 V ± 0.3V Parameter/Condition MDC fall time Symbol 1 Min Typ Max Unit Notes tMDHF — — 10 ns — Notes: 1.
USB Table 28. GPIO DC Electrical Characteristics (continued) Characteristic Symbol Condition Min Max Unit Input low voltage VIL — –0.3 0.8 V Input current IIN 0 V VIN NVDD — ±5 A 8.4.2 IEEE 1588 Timer AC Specifications This table provides the IEEE 1588 timer AC specifications. Table 29.
USB 9.1.2 USB AC Electrical Specifications This table lists the general timing parameters of the USB-ULPI interface. Table 31. USB General Timing Parameters Symbol 1 Min Max Unit Notes tUSCK 15 — ns 1, 2 Input setup to USB clock—all inputs tUSIVKH 4 — ns 1, 4 Input hold to USB clock—all inputs tUSIXKH 1 — ns 1, 4 USB clock to output valid—all outputs tUSKHOV — 9 ns 1 Output hold from USB clock—all outputs tUSKHOX 1 — ns 1 Parameter USB clock cycle time Notes: 1.
High-Speed Serial Interfaces (HSSI) 10 High-Speed Serial Interfaces (HSSI) This section describes the common portion of SerDes DC electrical specifications, which is the DC requirement for SerDes reference clocks. The SerDes data lane’s transmitter and receiver reference circuits are also shown. 10.1 Signal Terms Definition The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms used in the description and specification of differential signals.
High-Speed Serial Interfaces (HSSI) • Common Mode Voltage, Vcm The common mode voltage is equal to one-half of the sum of the voltages between each conductor of a balanced interchange circuit and ground. In this example, for SerDes output, Vcm_out = (VTXn + VTXn)/2 = (A + B) / 2, which is the arithmetic mean of the two complimentary output voltages within a differential pair. In a system, the common mode voltage may often differ from one component’s output to the other’s input.
High-Speed Serial Interfaces (HSSI) 10.2.1 SerDes Reference Clock Receiver Characteristics Figure 16 shows a receiver reference diagram of the SerDes reference clocks. • The supply voltage requirements for XCOREVDD are specified in Table 1 and Table 2. • SerDes reference clock receiver reference circuit structure — The SD_REF_CLK and SD_REF_CLK are internally AC-coupled differential inputs as shown in Figure 16.
High-Speed Serial Interfaces (HSSI) 10.2.2 DC Level Requirement for SerDes Reference Clocks The DC level requirement for the MPC8308 SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described below. • Differential Mode — The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-peak (or between 200 mV and 800 mV differential peak).
High-Speed Serial Interfaces (HSSI) 200 mV < Input Amplitude or Differential Peak < 800mV SD_REF_CLK Vmax < 80 0mV 100 mV < Vcm < 400 mV Vmin > 0 V SD_REF_CLK Figure 17. Differential Reference Clock Input DC Requirements (External DC-Coupled) 200mV < Input Amplitude or Differential Peak < 800mV SD_REF_CLK Vmax < Vcm + 400 mV Vcm Vmin > Vcm – 400 mV SD_REF_CLK Figure 18.
High-Speed Serial Interfaces (HSSI) NOTE Figure 20–Figure 23 are for conceptual reference only. Due to the fact that clock driver chip's internal structure, output impedance, and termination requirements are different between various clock driver chip manufacturers, it is very much possible that the clock circuit reference designs provided by clock driver chip vendor are different from what is shown below. They might also vary from one vendor to the other.
High-Speed Serial Interfaces (HSSI) MPC8308 LVDS CLK Driver Chip CLK_Out SD_REF_CLK 10 nF 50 SerDes Refer. CLK Receiver 100 differential PWB trace Clock Driver CLK_Out SD_REF_CLK 10 nF 50 Figure 21. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only) Figure 22 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.
High-Speed Serial Interfaces (HSSI) This figure shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC levels of the clock driver are compatible with the device’s SerDes reference clock input’s DC requirement. Single-Ended CLK Driver Chip MPC8308 Total 50 Assume clock driver’s output impedance is about 16 Clock Driver CLK_Out 50 SD_REF_CLK 33 SerDes Refer.
High-Speed Serial Interfaces (HSSI) Table 32. SerDes Reference Clock AC Parameters (continued) At recommended operating conditions with XCOREVDD= 1.0V ± 5% Parameter Rising edge rate (SD_REF_CLK) to falling edge rate (SD_REF_CLK) matching Symbol Min Max Unit Notes Rise-Fall Matching — 20 % 1, 4 Notes: 1. Measurement taken from single ended waveform. 2. Measurement taken from differential waveform. 3.
PCI Express 10.2.4.1 Spread Spectrum Clock SD_REF_CLK/SD_REF_CLK are not intended to be used with, and should not be clocked by, a spread spectrum clock source. 10.3 SerDes Transmitter and Receiver Reference Circuits This figure shows the reference circuits for SerDes data lane’s transmitter and receiver. TXn RXn 50 50 Transmitter Receiver 50 TXn 50 RXn Figure 26.
PCI Express 11.3 Clocking Dependencies The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance. 11.4 Physical Layer Specifications Following is a summary of the specifications for the physical layer of PCI Express on this device.
PCI Express Table 34.
PCI Express Table 34. Differential Transmitter (TX) Output Specifications (continued) Parameter AC coupling capacitor Crosslink random timeout Symbol Comments Min Typical Max CTX All Transmitters shall be AC coupled. The AC coupling is required either within the media or within the transmitting component itself. An external capacitor of 100nF is recommended.
PCI Express VTX-DIFF = 0 mV (D+ D– Crossing Point) VTX-DIFF = 0 mV (D+ D– Crossing Point) [Transition Bit] VTX-DIFFp-p-MIN = 800 mV [De-emphasized Bit] 566 mV (3 dB) >= VTX-DIFFp-p-MIN >= 505 mV (4 dB) 0.7 UI = UI – 0.3 UI(JTX-TOTAL-MAX) [Transition Bit] VTX-DIFFp-p-MIN = 800 mV Figure 27. Minimum Transmitter Timing and Voltage Output Compliance Specifications 11.4.
PCI Express Table 35. Differential Receiver (RX) Input Specifications (continued) Parameter Symbol AC peak common mode input voltage VRX-CM-ACp Comments Min Typical Max Units Note VPEACPCMRX = |VRXD+ + VRXD-|/2 VRX-CM-DC VRX-CM-DC = DC(avg) of |VRX-D+ + VRX-D-|/2 — — 150 mV 2 Differential return loss RLRX-DIFF Measured over 50 MHz to 1.25 GHz with the D+ and D- lines biased at +300 mV and -300 mV, respectively. 15 — — dB 4 Common mode return loss RLRX-CM Measured over 50 MHz to 1.
PCI Express Table 35. Differential Receiver (RX) Input Specifications (continued) Parameter Symbol Comments Min Typical Max Units Note Notes: 1. No test load is necessarily associated with this value. 2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 29 should be used as the RX device when taking measurements (also refer to the receiver compliance eye diagram shown in Figure 28).
Enhanced Local Bus NOTE The reference impedance for return loss measurements is 50 to ground for both the D+ and D- line (that is, as measured by a Vector Network Analyzer with 50 probes—see Figure 29). Note that the series capacitors, CPEACCTX, are optional for the return loss measurement. VRX-DIFF = 0 mV (D+ D– Crossing Point) VRX-DIFF = 0 mV (D+ D– Crossing Point) VRX-DIFFp-p-MIN > 175 mV 0.4 UI = TRX-EYE-MIN Figure 28. Minimum Receiver Eye Timing and Voltage Compliance Specification 11.5.
Enhanced Local Bus 12.1 Enhanced Local Bus DC Electrical Characteristics This table provides the DC electrical characteristics for the local bus interface. Table 36. Local Bus DC Electrical Characteristics at 3.3 V Parameter Symbol Min Max Unit High-level input voltage VIH 2.0 NVDD + 0.3 V Low-level input voltage VIL –0.3 0.8 V Input current, (VIN1 = 0 V or VIN = LVDD) IIN — ±5 A High-level output voltage, (LVDD = min, IOH = –2 mA) VOH NVDD – 0.
Enhanced Local Bus Figure 31 through Figure 33 show the local bus signals. In what follows, T1, T2, T3, and T4 are internal clock reference phase signals corresponding to LCCR[CLKDIV]. LCLK0 tLBIXKH tLBIVKH Input Signals: LD[0:15] tLBIXKH tLBIVKH Input Signal: LGTA tLBIXKH Output Signals: tLBKHOV LBCTL//LOE/ tLBKHOV tLBKHOZ Output Signals: LA[0:25] Figure 31.
Enhanced Secure Digital Host Controller (eSDHC) LCLK T1 T2 T3 T4 tLBKHOV tLBKHOZ GPCM Mode Output Signals: LCS[0:3]/LWE tLBIXKH tLBIVKH UPM Mode Input Signal: LUPWAIT tLBIXKH tLBIVKH Input Signals: LD[0:15] tLBKHOV tLBKHOZ UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] Figure 33.
Enhanced Secure Digital Host Controller (eSDHC) Table 38. eSDHC interface DC Electrical Characteristics (continued) Characteristic 13.2 Symbol Condition Min Max Unit Output low voltage VOL IOL = 3.2 mA — 0.4 V Input high voltage VIH — 2.1 NVDD + 0.3 V Input low voltage VIL — –0.3 0.8 V eSDHC AC Timing Specifications (Full Speed Mode) This section describes the AC electrical specifications for the eSDHC (SD/MMC) interface of the device.
Enhanced Secure Digital Host Controller (eSDHC) This figure provides the eSDHC clock input timing diagram. eSDHC External Clock operational mode VM VM VM tSFSCKL tSFSCKH tSFSCK VM = Midpoint Voltage (NVDD/2) tSFSCKR tSFSCKF Figure 34. eSDHC Clock Input Timing Diagram 13.2.1 Full Speed Output Path (Write) This figure provides the data and command output timing diagram.
Enhanced Secure Digital Host Controller (eSDHC) 13.2.2 Full Speed Input Path (Read) This figure provides the data and command input timing diagram. tSFSCK (Clock Cycle) SD CLK at the MPC8308 Pin Sampling Edge tCLK_DELAY SD CLK at the Card Pin Driving Edge tODLY tOH tDATA_DELAY Output from the SD Card Pins Input at the MPC8308 Pins tSFSIXKH tSFSIVKH (MPC8308 Input Hold) Figure 36. Full Speed Input Path 13.3 eSDHC AC Timing Specifications This table provides the eSDHC AC timing specifications.
Enhanced Secure Digital Host Controller (eSDHC) Table 40. eSDHC AC Timing Specifications for High Speed Mode (continued) At recommended operating conditions NVDD = 3.3 V ± 300 mV. Symbol 1 Min Max Unit Notes SD Card Output Valid tODLY — 14 ns 3 SD Card Output Hold tOH 2.
Enhanced Secure Digital Host Controller (eSDHC) 13.3.1 High Speed Output Path (Write) This figure provides the data and command output timing diagram. tSHSCK (Clock Cycle) SD CLK at the MPC8308 Pin Driving Edge tCLK_DELAY SD CLK at the Card Pin Sampling Edge Output Valid Time: tSHSKHOV tSHSCKL Output Hold Time: tSHSKHOX Output from the MPC8308 Pins Input at the SD Card Pins tDATA_DELAY tIH (2 ns) tISU (6 ns) Figure 38. High Speed Output Path 13.3.
JTAG 14 JTAG This section describes the DC and AC electrical specifications for the IEEE Std 1149.1™ (JTAG) interface. 14.1 JTAG DC Electrical Characteristics This table provides the DC electrical characteristics for the IEEE 1149.1 (JTAG) interface. Table 41. JTAG Interface DC Electrical Characteristics Characteristic 14.2 Symbol Condition Min Max Unit Input high voltage VIH — 2.1 NVDD + 0.3 V Input low voltage VIL — –0.3 0.
JTAG Table 42. JTAG AC Timing Specifications (Independent of SYS_CLK_IN) 1 (continued) At recommended operating conditions (see Table 2). Symbol2 Min Max Unit Note Boundary-scan data TDO tJTKLDX tJTKLOX 2 2 — — ns 5 JTAG external clock to output high impedance: Boundary-scan data TDO tJTKLDZ tJTKLOZ 2 2 19 9 ns 5, 6 Parameter Output hold times: Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question.
JTAG This figure provides the TRST timing diagram. TRST VM VM tTRST VM = Midpoint Voltage (NVDD/2) Figure 42. TRST Timing Diagram This figure provides the boundary-scan timing diagram. JTAG External Clock VM VM tJTDVKH tJTDXKH Boundary Data Inputs Input Data Valid tJTKLDV tJTKLDX Boundary Data Outputs Output Data Valid tJTKLDZ Boundary Data Outputs Output Data Valid VM = Midpoint Voltage (NVDD/2) Figure 43.
I2 C 15 I2C This section describes the DC and AC electrical characteristics for the I2C interface. 15.1 I2C DC Electrical Characteristics This table provides the DC electrical characteristics for the I2C interface. Table 43. I2C DC Electrical Characteristics At recommended operating conditions with NVDD of 3.3 V ± 0.3 V. Parameter Symbol Min Max Unit Notes Input high voltage level VIH 0.7 NVDD NVDD + 0.3 V — Input low voltage level VIL –0.3 0.
I2 C Table 44. I2C AC Electrical Specifications (continued) All values refer to VIH (min) and VIL (max) levels (see Table 43). Symbol1 Min Max Unit Setup time for STOP condition tI2PVKH 0.6 — s Bus free time between a STOP and START condition tI2KHDX 1.3 — s Noise margin at the LOW level for each connected device (including hysteresis) VNL 0.1 NVDD — V Noise margin at the HIGH level for each connected device (including hysteresis) VNH 0.2 NVDD — V Parameter Notes: 1.
Timers 16 Timers This section describes the DC and AC electrical specifications for the timers. 16.1 Timers DC Electrical Characteristics This table provides the DC electrical characteristics for the MPC8308 timers pins, including TIN, TOUT, and TGATE. Table 45. Timers DC Electrical Characteristics 16.2 Characteristic Symbol Condition Min Max Unit Output high voltage VOH IOH = –8.0 mA 2.4 — V Output low voltage VOL IOL = 8.0 mA — 0.5 V Output low voltage VOL IOL = 3.2 mA — 0.
GPIO 17 GPIO This section describes the DC and AC electrical specifications for the GPIO of MPC8308 17.1 GPIO DC Electrical Characteristics This table provides the DC electrical characteristics for the GPIO. Table 47. GPIO DC Electrical Characteristic Characteristic 17.2 Symbol Condition Min Max Unit Output high voltage VOH IOH = –8.0 mA 2.4 — V Output low voltage VOL IOL = 8.0 mA — 0.5 V Output low voltage VOL IOL = 3.2 mA — 0.4 V Input high voltage VIH — 2.1 NVDD + 0.
IPIC 18 IPIC This section describes the DC and AC electrical specifications for the external interrupt pins. 18.1 IPIC DC Electrical Characteristics This table provides the DC electrical characteristics for the external interrupt pins. Table 49. IPIC DC Electrical Characteristics Characteristic 18.2 Symbol Condition Min Max Unit Input high voltage VIH — 2.1 NVDD + 0.3 V Input low voltage VIL — –0.3 0.8 V Input current IIN — — ±5 A Output high voltage VOH IOH = –8.0 mA 2.
SPI Table 51. SPI DC Electrical Characteristics (continued) 19.2 Characteristic Symbol Condition Min Max Unit Output high voltage VOH IOH = –8.0 mA 2.4 — V Output low voltage VOL IOL = 8.0 mA — 0.5 V Output low voltage VOL IOL = 3.2 mA — 0.4 V SPI AC Timing Specifications This table and provide the SPI input and output AC timing specifications. Table 52.
Package and Pin Listings This figure shows the SPI timing in slave mode (external clock). SPICLK (input) Input Signals: SPIMOSI (See Note) tNEIVKH tNEIXKH tNEKHOV Output Signals: SPIMISO (See Note) Note: The clock edge is selectable on SPI. Figure 50. SPI AC Timing in Slave Mode (External Clock) Diagram This figure shows the SPI timing in master mode (internal clock).
Package and Pin Listings 20.2 Mechanical Dimensions of the MPC8308 MAPBGA This figure shows the mechanical dimensions and bottom surface nomenclature of the MAPBGA package. Figure 52. Mechanical Dimension and Bottom Surface Nomenclature of the MPC8308 MAPBG Notes: 1. All dimensions are in millimeters. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev.
Package and Pin Listings 2. Dimensions and tolerances per ASME Y14.5M-1994. 3. Maximum solder ball diameter measured parallel to datum A. 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 20.3 Pinout Listings This table provides the pin-out listing for the MPC8308, MAPBGA package. Table 53.
Package and Pin Listings Table 53.
Package and Pin Listings Table 53.
Package and Pin Listings Table 53.
Package and Pin Listings Table 53.
Package and Pin Listings Table 53.
Package and Pin Listings Table 53.
Package and Pin Listings Table 53.
Package and Pin Listings Table 53.
Package and Pin Listings Table 53.
Clocking 21 Clocking This figure shows the internal distribution of clocks within the device.
Clocking 21.1 System Clock Domains The primary clock input (SYS_CLK_IN) frequency is multiplied up by the system phase-locked loop (PLL) and the clock unit to create three major clock domains: • The coherent system bus clock (csb_clk) • The internal clock for the DDR controller (ddr_clk) • The internal clock for the local bus interface unit (lbc_clk) The csb_clk frequency is derived as follows: csb_clk = [SYS_CLK_IN] × SPMF The csb_clk serves as the clock input to the e300 core.
Clocking This table provides the operating frequencies for the device under recommended operating conditions (Table 2). Table 55. Operating Frequencies for MPC8308 Characteristic1 Maximum Operating Frequency Unit e300 core frequency (core_clk) 400 MHz Coherent system bus frequency (csb_clk) 133 MHz DDR2 memory bus frequency (MCK)2 133 MHz 66 MHz Local bus frequency (LCLK0) 3 Notes: 1.
Thermal 21.3 Core PLL Configuration RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300 core clock (core_clk). This table shows the encodings for RCWL[COREPLL]. COREPLL values that are not listed in this table should be considered as reserved. NOTE Core VCO frequency = core frequency VCO divider. The VCO divider, which is determined by RCWLR[COREPLL], must be set properly so that the core VCO frequency is in the range of 400–800 MHz. Table 58.
Thermal 22.1 Thermal Characteristics This table provides the package thermal characteristics for the 473, 19 19 mm MAPBGA. Table 59.
Thermal appropriate for a tightly packed printed-circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. Test cases have demonstrated that errors of a factor of two (in the quantity TJ – TA) are possible. 22.2.
System Design Information 23 System Design Information This section provides electrical and thermal design recommendations for successful application of the device 23.1 System Clocking The device includes two PLLs. 1. The platform PLL generates the platform clock from the externally supplied SYS_CLK_IN input. The frequency ratio between the platform and SYS_CLK_IN is selected using the platform PLL ratio configuration bits as described in Section 21.2, “System PLL Configuration.” 2.
System Design Information 23.3 Decoupling Recommendations Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC8308 system, and the MPC8308 itself requires a clean, tightly regulated source of power.
System Design Information NVDD RN SW2 Pad Data SW1 RP VSS Figure 55. Driver Impedance Measurement The value of this resistance and the strength of the driver’s current source can be found by making two measurements. First, the output voltage is measured while driving logic 1 without an external differential termination resistor. The measured voltage is V1 = Rsource Isource.
Ordering Information 23.7 Pull-Up Resistor Requirements The device requires high resistance pull-up resistors (10 k is recommended) on open drain type pins including I2C, Ethernet management MDIO, HRESET and IPIC (integrated programmable interrupt controller). Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 56.
Ordering Information 24.2 Part Marking Parts are marked as in the example shown in this figure. MPCnnnnCVMADDA core/platform MHZ ATWLYYWW CCCCC *MMMMM YWWLAZ PBGA Notes: ATWLYYWW is the traceability code. CCCCC is the country code. MMMMM is the mask number. YWWLAZ is the assembly traceability code. Figure 56. Freescale Part Marking for PBGA Devices This table lists the SVR settings. Table 62. SVR Settings Device Package SVR MPC8308 MAPBGA 0x8101 _0110 Note: PVR = 8085_0020 for the device.
Document Revision History 25 Document Revision History This table summarizes a revision history for this document. Table 63. Document Revision History Rev. Number Date 3 10/2011 • • • • 2 02/2011 • Added NVDDJ to Note-7 in Table 1.
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