Datasheet

MPC8250 Hardware Specifications, Rev. 2
4 Freescale Semiconductor
Features
Dedicated interface logic for SDRAM
CPU core can be disabled and the device can be used in slave mode to an external core
Communications processor module (CPM)
Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support
for communications protocols
Interfaces to G2 core through on-chip 32-Kbyte dual-port RAM and DMA controller
Serial DMA channels for receive and transmit on all serial channels
Parallel I/O registers with open-drain and interrupt capability
Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
Three fast communications controllers supporting the following protocols:
10/100-Mbit Ethernet/IEEE 802.3® CDMA/CS interface through media independent
interface (MII)
Transparent
HDLC—Up to T3 rates (clear channel)
One multichannel controller (MCC2)
Handles 128 serial, full-duplex, 64-Kbps data channels. The MCC can be split into four
subgroups of 32 channels each.
Almost any combination of subgroups can be multiplexed to single or multiple TDM
interfaces up to four TDM interfaces per MCC
Four serial communications controllers (SCCs) identical to those on the MPC860, supporting
the digital portions of the following protocols:
Ethernet/IEEE 802.3 CDMA/CS
HDLC/SDLC and HDLC bus
Universal asynchronous receiver transmitter (UART)
Synchronous UART
Binary synchronous (BISYNC) communications
Transparent
Two serial management controllers (SMCs), identical to those of the MPC860
Provide management for BRI devices as general circuit interface (GCI) controllers in time-
division-multiplexed (TDM) channels
Transparent
UART (low-speed operation)
One serial peripheral interface identical to the MPC860 SPI
One inter-integrated circuit (I
2
C) controller (identical to the MPC860 I
2
C controller)
Microwire compatible
Multiple-master, single-master, and slave modes
Up to four TDM interfaces
Supports one group of four TDM channels