Datasheet

MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor 15
Electrical and Thermal Characteristics
Figure 6 shows the SCC/SMC/SPI/I
2
C internal clock.
Figure 6. SCC/SMC/SPI/I
2
C Internal Clock Diagram
Figure 7 shows TDM input and output signals.
Figure 7. TDM Signal Diagram
BRG_OUT
SCC/SMC/SPI/I2C input signals
SCC/SMC/SPI/I2C output signals
sp18a
sp19a
sp38a/sp39a
(See note.)
(See note.)
Note: There are four possible timing conditions for SCC and SPI:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
Serial CLKin
TDM input signals
TDM output signals
sp20
sp21
sp40/sp41
Note: There are four possible TDM timing conditions:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.