Freescale Semiconductor Document Number: MPC8250EC Rev. 2, 07/2009 MPC8250 Hardware Specifications This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC8250 PowerQUICC II™ communications processor.
Features Figure 1 shows the block diagram for the MPC8250.
Features • • • • • • • — Supports bus snooping for data cache coherency — Floating-point unit (FPU) Separate power supply for internal logic (1.8 V) and for I/O (3.3V) Separate PLLs for G2 core and for the CPM — G2 core and CPM can run at different frequencies for power/performance optimization — Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios — Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.
Features • • — Dedicated interface logic for SDRAM CPU core can be disabled and the device can be used in slave mode to an external core Communications processor module (CPM) — Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support for communications protocols — Interfaces to G2 core through on-chip 32-Kbyte dual-port RAM and DMA controller — Serial DMA channels for receive and transmit on all serial channels — Parallel I/O registers with open-drain and interrupt capab
Features – – – – • 2,048 bytes of SI RAM Bit or byte resolution Independent transmit and receive routing, frame synchronization Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN primary rate, Freescale interchip digital link (IDL), general circuit interface (GCI), and user-defined TDM serial interfaces — Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs, SCCs, SMCs, and serial channels — Four independent 16-bit timers that can
Electrical and Thermal Characteristics 2 Electrical and Thermal Characteristics This section provides AC and DC electrical specifications and thermal characteristics for the MPC8250. 2.1 DC Electrical Characteristics This section describes the DC electrical characteristics for the MPC8250. Table 1 shows the maximum electrical ratings. Table 1. Absolute Maximum Ratings 1 Rating Core supply voltage 2 Value Unit VDD -0.3 – 2.5 V 2 VCCSYN -0.3 – 2.5 V 3 VDDH -0.3 – 4.0 V VIN GND(-0.3) – 3.
Electrical and Thermal Characteristics NOTE: Core, PLL, and I/O Supply Voltages VDDH, VCCSYN, and VDD must track each other and both must vary in the same direction—in the positive direction (+5% and +0.1 Vdc) or in the negative direction (-5% and -0.1 Vdc).
Electrical and Thermal Characteristics Table 3. DC Electrical Characteristics 1 (continued) Characteristic IOL = 7.
Electrical and Thermal Characteristics Table 3. DC Electrical Characteristics 1 (continued) Characteristic IOL = 5.
Electrical and Thermal Characteristics 1 The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input. To prevent excessive DC current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs. 2 The leakage current is measured for nominal VDD, VCCSYN, and VDD. 2.2 Thermal Characteristics Table 4 describes thermal characteristics. Table 4.
Electrical and Thermal Characteristics where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. 2.3.1 Layout Practices Each VCC pin should be provided with a low-impedance path to the board’s power supply. Each ground pin should likewise be provided with a low-impedance path to ground.
Electrical and Thermal Characteristics 2.4 AC Electrical Characteristics The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and inputs for the 66 MHz MPC8250 device. Note that AC timings are based on a 50-pf load. Typical output buffer impedances are shown in Table 6. Table 6. Output Buffer Impedances 1 Output Buffers Typical Impedance (Ω) 60x bus 40 Local bus 40 Memory controller 40 Parallel I/O 46 PCI 25 1 These are typical values at 65° C.
Electrical and Thermal Characteristics Table 8.
Electrical and Thermal Characteristics Figure 4 shows the FCC internal clock. BRG_OUT sp17a sp16a FCC input signals sp36a/sp37a FCC output signals Note: When GFMR.TCI = 0 sp36a/sp37a FCC output signals Note: When GFMR.TCI = 1 Figure 4. FCC Internal Clock Diagram Figure 5 shows the SCC/SMC/SPI/I2C external clock. Serial CLKin sp18b sp19b SCC/SMC/SPI/I2C input signals (See note.) sp38b/sp39b SCC/SMC/SPI/I2C output signals (See note.) Note: There are four possible timing conditions for SCC and SPI: 1.
Electrical and Thermal Characteristics Figure 6 shows the SCC/SMC/SPI/I2C internal clock. BRG_OUT sp19a sp18a SCC/SMC/SPI/I2C input signals (See note.) sp38a/sp39a SCC/SMC/SPI/I2C output signals (See note.) Note: There are four possible timing conditions for SCC and SPI: 1. Input sampled on the rising edge and output driven on the rising edge (shown). 2. Input sampled on the rising edge and output driven on the falling edge. 3. Input sampled on the falling edge and output driven on the falling edge. 4.
Electrical and Thermal Characteristics Figure 8 shows PIO, timer, and DMA signals. Sys clk sp23 sp22 PIO/IDMA/TIMER[TGATE assertion] input signals (See note) sp23 sp22 TIMER input signal [TGATE deassertion] (See note) sp42/sp43 IDMA output signals sp42/sp43 sp42a/sp43a TIMER(sp42/43)/ PIO(sp42a/sp43a) output signals Note: TGATE is asserted on the rising edge of the clock; it is deasserted on the falling edge. Figure 8. PIO, Timer, and DMA Signal Diagram Table 9 lists SIU input characteristics.
Electrical and Thermal Characteristics Table 10 lists SIU output characteristics. Table 10. AC Characteristics for SIU Outputs 1 Spec Number Max Delay (ns) Min Delay (ns) Characteristic 1 Max Min 66 MHz 83 MHz 66 MHz 83 MHz sp31 sp30 PSDVAL/TEA/TA 7 6 0.5 0.5 sp32 sp30 ADD/ADD_atr./BADDR/CI/GBL/WT 8 6.5 0.5 0.5 sp33a sp30 Data bus 6.5 6.5 0.5 0.5 sp33b sp30 DP 8 7 0.5 0.5 sp34 sp30 Memory controller signals/ALE 6 5 0.5 0.5 sp35 sp30 All other signals 6 5.5 0.
Electrical and Thermal Characteristics Figure 9 shows the interaction of several bus signals. CLKin sp11 sp10 AACK/ARTRY/TA/TS/TEA/ DBG/BG/BR input signals sp12 sp10 sp15 sp10 DATA bus normal mode input signal All other input signals sp30 sp31 PSDVAL/TEA/TA output signals sp32 sp30 sp33a sp30 sp35 sp30 ADD/ADD_atr/BADDR/CI/ GBL/WT output signals DATA bus output signals All other output signals Figure 9.
Electrical and Thermal Characteristics Figure 11 shows signal behavior in MEMC mode. CLKin V_CLK sp34/sp30 Memory controller signals Figure 11. MEMC Mode Diagram NOTE Generally, all MPC8250 bus and system output signals are driven from the rising edge of the input clock (CLKin). Memory controller signals, however, trigger on four points within a CLKin cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge, and T3 at the falling edge, of CLKin.
Clock Configuration Modes NOTE The UPM machine outputs change on the internal tick determined by the memory controller programming; the AC specifications are relative to the internal tick. Note that SDRAM and GPCM machine outputs change on CLKin’s rising edge. 3 Clock Configuration Modes The MPC8250 has three clocking modes: local, PCI host, and PCI agent. The clocking mode is set according to three input pins—PCI_MODE, PCI_CFG[0], PCI_MODCK—as shown in Table 12. Table 12.
Clock Configuration Modes Table 13. Clock Default Configurations MODCK[1–3] Input Clock Frequency CPM Multiplication Factor CPM Frequency Core Multiplication Factor Core Frequency 100 66 MHz 2 133 MHz 2.5 166 MHz 101 66 MHz 2 133 MHz 3 200 MHz 110 66 MHz 2.5 166 MHz 2.5 166 MHz 111 66 MHz 2.5 166 MHz 3 200 MHz Table 14 describes all possible clock configurations when using the hard reset configuration sequence. Note also that basic modes are shown in boldface type.
Clock Configuration Modes Table 14.
Clock Configuration Modes Table 14. Clock Configuration Modes 1 (continued) MODCK_H–MODCK[1–3] Input Clock CPM Multiplication Frequency2, 3 Factor2 Core Multiplication CPM Core Factor2 Frequency2 Frequency2 0111_001 66 MHz 3 200 MHz 2 133 MHz 0111_010 66 MHz 3 200 MHz 2.5 166 MHz 0111_011 66 MHz 3 200 MHz 3 200 MHz 0111_100 66 MHz 3 200 MHz 3.5 233 MHz 0111_101 66 MHz 3 200 MHz 4 266 MHz 0111_110 66 MHz 3 200 MHz 4.5 300 MHz 0111_111 66 MHz 3.
Clock Configuration Modes 3.2.1 PCI Host Mode The frequencies listed in Table 15 are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user’s device. Table 15.
Clock Configuration Modes Table 16. Clock Configuration Modes in PCI Host Mode (continued) MODCK_H – MODCK[1– 3] Input Clock Frequency 1 (Bus) 0011_0103 33 MHz 5 166 MHz 7 233 MHz 5 33 MHz 0011_0113 33 MHz 5 166 MHz 8 266 MHz 5 33 MHz 0100_0003 33 MHz 6 200 MHz 5 166 MHz 6 33 MHz 3 33 MHz 6 200 MHz 6 200 MHz 6 33 MHz 0100_0103 33 MHz 6 200 MHz 7 233 MHz 6 33 MHz 0100_0113 33 MHz 6 200 MHz 8 266 MHz 6 33 MHz 0101_000 66 MHz 2 133 MHz 2.
Clock Configuration Modes Table 16. Clock Configuration Modes in PCI Host Mode (continued) MODCK_H – MODCK[1– 3] Input Clock Frequency 1 (Bus) 1001_001 66 MHz 3.5 233 MHz 3 200 MHz 4/8 58/29 MHz 1001_010 66 MHz 3.5 233 MHz 3.5 233 MHz 4/8 58/29 MHz 1001_011 66 MHz 3.5 233 MHz 4 266 MHz 4/8 58/29 MHz 1001_100 66 MHz 3.5 233 MHz 4.5 300 MHz 4/8 58/29 MHz 1010_000 100 MHz 2 200 MHz 2 200 MHz 3/6 66/33 MHz 1010_001 100 MHz 2 200 MHz 2.
Clock Configuration Modes Table 17. Clock Default Configurations in PCI Agent Mode (MODCK_HI = 0000) Core Input Clock CPM Core CPM Bus Division 60x Bus Multiplication MODCK[1–3]1 Frequency Multiplication 3 Frequency Frequency Factor Frequency 4 Factor (PCI)2 Factor 2 100 66/33 MHz 3/6 200 MHz 3 240 MHz 2.5 80 MHz 101 66/33 MHz 3/6 200 MHz 3.5 280 MHz 2.5 80 MHz 110 66/33 MHz 4/8 266 MHz 3.5 300 MHz 3 88 MHz 111 66/33 MHz 4/8 266 MHz 3 300 MHz 2.
Clock Configuration Modes Table 18. Clock Configuration Modes in PCI Agent Mode (continued) MODCK_H Input Clock Core CPM Core – CPM Bus Division 60x Bus Frequency Multiplication Multiplication Frequency 3 MODCK[1– Frequency Factor Frequency 4 1, 2 1 (PCI) Factor Factor 3] 0100_011 66/33 MHz 3/6 200 MHz 4 266 MHz 3 66 MHz 0100_100 66/33 MHz 3/6 200 MHz 4.5 300 MHz 3 66 MHz 0101_000 5 33 MHz 5 166 MHz 2.5 166 MHz 2.5 66 MHz 5 0101_001 33 MHz 5 166 MHz 3 200 MHz 2.
Pinout Table 18. Clock Configuration Modes in PCI Agent Mode (continued) MODCK_H Input Clock Core CPM Core – CPM Bus Division 60x Bus Frequency Multiplication Multiplication Frequency 3 MODCK[1– Frequency Factor Frequency 4 1, 2 1 (PCI) Factor Factor 3] 1 2 3 4 5 4 1010_000 66/33 MHz 4/8 266 MHz 2.5 222 MHz 3 88 MHz 1010_001 66/33 MHz 4/8 266 MHz 3 266 MHz 3 88 MHz 1010_010 66/33 MHz 4/8 266 MHz 3.
Pinout 4.1.1 TBGA Pin Assignments Figure 13 shows the pinout of the TBGA package as viewed from the top surface. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 A A B B C C D E D E F F G H G H J J K K L M L M N N P R P R T U T U V V W W Y AA Y AA AB AB AC AC AD AE AD AE AF AF AG AH AG AH AJ AJ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Not to Scale Figure 13.
Pinout Figure 14 shows the side profile of the TBGA package to indicate the direction of the top surface view. View Copper Heat Spreader (Oxidized for Insulation) Etched Cavity Die Attach Polymide Tape Pressure Sensitive Adhesive Die Soldermask Glob-Top Filled Area Glob-Top Dam Copper Traces 1.27 mm Pitch Wire Bonds Figure 14. Side View of the TBGA Package Table 20 shows the pinout list of the TBGA package of the MPC8250. Table 19 defines the conventions and acronyms used in Table 20. Table 19.
Pinout Table 20. MPC8250 TBGA Package Pinout List (continued) Pin Name Ball A13 L5 A14 L4 A15 L3 A16 L2 A17 L1 A18 M5 A19 N5 A20 N4 A21 N3 A22 N2 A23 N1 A24 P4 A25 P3 A26 P2 A27 P1 A28 R1 A29 R3 A30 R5 A31 R4 TT0 F1 TT1 G4 TT2 G3 TT3 G2 TT4 F2 TBST D3 TSIZ0 C1 TSIZ1 E4 TSIZ2 D2 TSIZ3 F5 AACK F3 ARTRY E1 DBG V1 DBB/IRQ3 V2 D0 B20 D1 A18 MPC8250 Hardware Specifications, Rev.
Pinout Table 20. MPC8250 TBGA Package Pinout List (continued) Pin Name Ball D2 A16 D3 A13 D4 E12 D5 D9 D6 A6 D7 B5 D8 A20 D9 E17 D10 B15 D11 B13 D12 A11 D13 E9 D14 B7 D15 B4 D16 D19 D17 D17 D18 D15 D19 C13 D20 B11 D21 A8 D22 A5 D23 C5 D24 C19 D25 C17 D26 C15 D27 D13 D28 C11 D29 B8 D30 A4 D31 E6 D32 E18 D33 B17 D34 A15 D35 A12 D36 D11 MPC8250 Hardware Specifications, Rev.
Pinout Table 20.
Pinout Table 20.
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Pinout 4.2.1 PBGA Pin Assignments Figure 15 shows the pinout of the PBGA package as viewed from the top surface. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A A B B C D C D E E F G F G H H J J K L K L M M N N P R P R T U T U V V W Y W Y AA AA AB AB AC AD AC AD AE AE AF AF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Not to Scale Figure 15.
Pinout Figure 16 shows the side profile of the PBGA package to indicate the direction of the top surface view. Die attach Transfer molding compound Wire bonds Ball bond Screen-printed solder mask Plated substrate via Cu substrate traces DIE BT resin glass epoxy 1 mm pitch Figure 16. Side View of the PBGA Package Table 22 shows the pinout list of the PBGA package of the MPC8250. Table 21 defines conventions and acronyms used in Table 22. Table 21.
Pinout Table 22. MPC8250 PBGA Package Pinout List (continued) Pin Name Ball A14 F11 A15 B7 A16 B8 A17 C9 A18 A7 A19 B9 A20 E11 A21 A8 A22 D11 A23 B10 A24 C11 A25 A9 A26 B11 A27 C12 A28 D12 A29 A10 A30 B12 A31 B13 TT0 E7 TT1 B3 TT2 F8 TT3 A3 TT4 C3 TBST F5 TSIZ0 E3 TSIZ1 E2 TSIZ2 E1 TSIZ3 E4 AACK D3 ARTRY C2 DBG A14 DBB/IRQ3 C15 D0 W4 D1 Y1 D2 V1 MPC8250 Hardware Specifications, Rev.
Pinout Table 22. MPC8250 PBGA Package Pinout List (continued) Pin Name Ball D3 P4 D4 N3 D5 K5 D6 J4 D7 G1 D8 AB1 D9 U4 D10 U2 D11 N6 D12 N1 D13 L1 D14 J5 D15 G3 D16 AA2 D17 W1 D18 T3 D19 T1 D20 M2 D21 K2 D22 J1 D23 G4 D24 U5 D25 T5 D26 P5 D27 P3 D28 M3 D29 K3 D30 H2 D31 G5 D32 AA1 D33 V2 D34 U1 D35 P2 D36 M4 D37 K4 MPC8250 Hardware Specifications, Rev.
Pinout Table 22.
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Package Description Table 22.
Package Description 5.1 Package Parameters Package parameters are provided in Table 23. Table 23. Package Parameters Package ZU Devices MPC8250 Outline (mm) Type Interconnects Pitch (mm) Nominal Unmounted Height (mm) 37.5 × 37.5 TBGA 480 1.27 1.55 516 1 2.25 VV ZO VR 5.2 TBGA (Pb free) 27 × 27 PBGA PBGA (Pb free) Mechanical Dimensions This section discusses the TBGA and PBGA package dimensions. MPC8250 Hardware Specifications, Rev.
Package Description 5.2.1 TBGA Package Dimensions Figure 17 provides the mechanical dimensions and bottom surface nomenclature of the 480 TBGA package. Notes: 1. Dimensions and Tolerancing per ASME Y14.5M-1994. 2. Dimensions in millimeters. 3. Dimension b is measured at the Millimeters Dim Min Max A 1.45 1.65 A1 0.60 0.70 A2 0.85 0.95 A3 0.25 — b 0.65 0.85 D 37.50 BSC D1 35.56 REF e 1.27 BSC E 37.50 BSC E1 35.56 REF Figure 17.
Package Description 5.2.2 PBGA Package Dimensions Figure 18 provides the mechanical dimensions and bottom surface nomenclature of the 516 PBGA package. Figure 18. Mechanical Dimensions and Bottom Surface Nomenclature—516 PBGA MPC8250 Hardware Specifications, Rev.
Ordering Information 6 Ordering Information Figure 19 provides an example of the Freescale part numbering nomenclature for the MPC8250. In addition to the processor frequency, the part numbering scheme also consists of a part modifier that indicates any enhancement(s) in the part from the original production design. Each part number also contains a revision code that refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only.
Document Revision History Table 24. Document Revision History (continued) Revision Date Substantive Changes 0.6 10/2002 Table 22, “VR Pinout”: corrected ball assignment for the following pins—A12–A17, TA, PD5, PC2. 0.5 9/2002 Addition of VR (516 PBGA) package information. Refer to sections 2.2, 4.2, and 5. 0.4 5/2002 • • • • • 0.3 3/2002 • Table 20: modified note to pin AF25. 0.2 3/2202 • Table 20: modified notes to pins AE11 and AF25.
Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC8250 Hardware Specifications, Rev.
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