Datasheet

MPC5200B Data Sheet, Rev. 4
54 Freescale Semiconductor
Figure 44. Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1)
1.3.17 GPIOs and Timers
1.3.17.1 General and Asynchronous Signals
The MPC5200B contains several sets if I/Os that do not require special setup, hold, or valid requirements. Most of these are
asynchronous to the system clock. The following numbers are provided for test and validation purposes only, and they assume
a 133 MHz internal bus frequency.
Figure 45 shows the GPIO Timing Diagram. Table 50 gives the timing specifications.
Table 50. Asynchronous Signals
Sym Description Min Max Units SpecID
t
CK
Clock Period 7.52 — ns A16.1
t
IS
Input Setup 12 — ns A16.2
t
IH
Input Hold 1 — ns A16.3
t
DV
Output Valid — 15.33 ns A16.4
t
DH
Output Hold 1 — ns A16.5
SCK
(CLKPOL=0)
SCK
(CLKPOL=1)
MOSI
Input
Input
Input
SS
Input
MISO
Output
1
22
7
8
3
4
6
5