Datasheet

MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor 53
Figure 43. Timing Diagram — SPI Master Mode, Format 1 (CPHA = 1)
NOTE
Output timing is specified at a nominal 50 pF load.
Table 49. Timing Specifications — SPI Slave Mode, Format 1 (CPHA = 1)
Sym Description Min Max Units SpecID
1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A15.56
2 SCK pulse width, 50% SCK duty cycle 15.0 — ns A15.57
3 Slave select clock delay 0.0 — ns A15.58
4 Output data valid — 14.0 ns A15.59
5 Input Data setup time 2.0 — ns A15.60
6 Input Data hold time 1.0 — ns A15.61
7 Slave disable lag time 0.0 — ns A15.62
8 Minimum Sequential Transfer delay = 2 × IP-Bus clock cycle time 30.0 — ns A15.63
SCK
(CLKPOL=0)
SCK
(CLKPOL=1)
MOSI
Output
Output
Output
SS
Output
MISO
Input
1
22
7
8
3
4
6
10
9
9
10
5