Datasheet

MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor 51
Figure 41. Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0)
NOTE
Output timing is specified at a nominal 50 pF load.
Table 47. Timing Specifications — SPI Slave Mode, Format 0 (CPHA = 0)
Sym Description Min Max Units SpecID
1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A15.37
2 SCK pulse width, 50% SCK duty cycle 15.0 — ns A15.38
3 Slave select clock delay 1.0 — ns A15.39
4 Input Data setup time 1.0 — ns A15.40
5 Input Data hold time 1.0 — ns A15.41
6 Output data valid after SS
— 14.0 ns A15.42
7 Output data valid after SCK — 14.0 ns A15.43
8 Slave disable lag time 0.0 — ns A15.44
9 Minimum Sequential Transfer delay = 2 × IP Bus clock cycle time 30.0 — — A15.45
SCK
(CLKPOL=0)
SCK
(CLKPOL=1)
MOSI
Output
Output
Output
SS
Output
MISO
Input
1
22
8
9
3
4
5
6
6
7
7
11
10
10
11