Datasheet

MPC5200B Data Sheet, Rev. 4
48 Freescale Semiconductor
NOTE
Output timing is specified at a nominal 50 pF load.
Figure 38. Timing Diagram — 8-, 16-, 24-, and 32-bit CODEC / I
2
S Slave Mode
Table 43. Timing Specifications — 8-, 16-, 24-, and 32-bit CODEC / I
2
S Slave Mode
Sym Description Min Typ Max Units SpecID
1 Bit Clock cycle time 40.0 — — ns A15.9
2 Clock duty cycle — 50 — %
(1)
1
Bit Clock cycle time.
A15.10
3 FrameSync setup time 1.0 — — ns A15.11
4 Output Data valid after clock edge — — 14.0 ns A15.12
5 Input Data setup time 1.0 — — ns A15.13
6 Input Data hold time 1.0 — — ns A15.14
BitClk
3
(CLKPOL=0)
BitClk
(CLKPOL=1)
FrameSync
(SyncPol = 1)
TxD
Output
Input
Input
4
5
Input
FrameSync
(SyncPol = 0)
Input
RxD
Input
1
22
6