Datasheet

MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor 45
Figure 35. Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1)
1.3.13 MSCAN
The CAN functions are available as RX and TX pins at normal IO pads (I
2
C1+GPTimer or PSC2). There is no filter for the
WakeUp dominant pulse. Any High-to-Low edge can cause WakeUp, if configured.
1.3.14 I
2
C
Table 40. I
2
C Input Timing Specifications—SCL and SDA
Sym Description Min Max Units SpecID
1 Start condition hold time 2 — IP-Bus Cycle
(1)
1
Inter Peripheral Clock is defined in the MPC5200B User’s Manual (MPC5200BUM).
A13.1
2 Clock low time 8 — IP-Bus Cycle
(1)
A13.2
4 Data hold time 0.0 — ns A13.3
6 Clock high time 4 — IP-Bus Cycle
(1)
A13.4
7 Data setup time 0.0 — ns A13.5
8 Start condition setup time (for repeated start condition
only)
2 — IP-Bus Cycle
(1)
A13.6
9 Stop condition setup time 2 — IP-Bus Cycle
(1)
A13.7
SCK
(CLKPOL=0)
SCK
(CLKPOL=1)
MOSI
Input
Input
Input
SS
Input
MISO
Output
1
22
7
8
3
4
6
5