Datasheet

MPC5200B Data Sheet, Rev. 4
38 Freescale Semiconductor
Figure 26. Timing Diagram—ATA-ISOLATION
1.3.10 Ethernet
AC Test Timing Conditions:
• Output Loading
All Outputs: 25 pF
Figure 27. Ethernet Timing Diagram—MII Rx Signal
Table 30. Timing Specification ata_isolation
Sym Description Min Max Units SpecID
1 ata_isolation setup time 7
— IP Bus cycles A8.48
2 ata_isolation hold time
— 19 IP Bus cycles A8.49
Table 31. MII Rx Signal Timing
Sym Description Min Max Unit SpecID
t
1
RXD[3:0], RX_DV, RX_ER to RX_CLK setup 10 — ns A9.1
t
2
RX_CLK to RXD[3:0], RX_DV, RX_ER hold 10 — ns A9.2
t
3
RX_CLK pulse width high 35% 65% RX_CLK Period
(1)
1
RX_CLK shall have a frequency of 25% of data rate of the received signal. See the IEEE 802.3 Specification.
A9.3
t
4
RX_CLK pulse width low 35% 65% RX_CLK Period
(1)
A9.4
DIOR
2
1
ATA_ IS OLAT ION
t
4
t
3
t
1
t
2
RX_CLK (Input)
RXD[3:0] (inputs)
RX_DV
RX_ER