Datasheet

MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor 31
Figure 15. Multiword DMA Timing
NOTE
The direction of signal assertion is towards the top of the page, and the direction of negation
is towards the bottom of the page, irrespective of the electrical properties of the signal.
Table 29. Ultra DMA Timing Specification
Sym
MODE 0
(ns)
MODE 1
(ns)
MODE 2
(ns)
Comment SpecID
Min Max Min Max Min Max
t
CYC
114 — 75 — 55 — Cycle time allowing for asymmetry and clock
variations from STROBE edge to STROBE edge
A8.26
t
2CYC
235 — 156 — 117 — Two-cycle time allowing for clock variations, from
rising edge to next rising edge or from falling edge to
next falling edge of STROBE.
A8.27
t
DS
15 — 10 — 7 — Data setup time at recipient. A8.28
t
DH
5—5—5— Data hold time at recipient. A8.29
t
DVS
70 — 48 — 34 — Data valid setup time at sender, to STROBE edge. A8.30
t
DVH
6 — 6 — 6 — Data valid hold time at sender, from STROBE edge. A8.31
t
FS
0 230 0 200 0 170 First STROBE time for drive to first negate DSTROBE
from STOP during a data-in burst.
A8.32
t
LI
015001500150 Limited Interlock time. A8.33
t
MLI
20 — 20 — 20 — Interlock time with minimum. A8.34
t
UI
0—0—0— Unlimited interlock time. A8.35
t
0
t
C
t
E
t
I
t
D
t
F
t
H
t
G
t
J
DMARQ
RDATA
WDATA
(Drive)
(Host)
(Host)
(Drive)
(Host)
t
L
t
K
DMACK
DIOR
DIOW