Datasheet
MPC5200B Data Sheet, Rev. 4
30 Freescale Semiconductor
Figure 14. PIO Mode Timing
Table 28. Multiword DMA Timing Specifications
Sym Multiword DMA Timing Parameters Min/Max Mode 0(ns) Mode 1(ns) Mode 2(ns) SpecID
t
0
Cycle Time min 480 150 120 A8.12
t
C
DMACK to DMARQ delay max — — — A8.13
t
D
DIOR/DIOW pulse width (16-bit) min 215 80 70 A8.14
t
E
DIOR data access max 150 60 50 A8.15
t
G
DIOR/DIOW data setup min 100 30 20 A8.16
t
F
DIOR data hold min 5 5 5 A8.17
t
H
DIOW data hold min 20 15 10 A8.18
t
I
DMACK to DIOR/DIOW setup min 0 0 0 A8.19
t
J
DIOR/DIOW to DMACK hold min 20 5 5 A8.20
t
Kr
DIOR negated pulse width min 50 50 25 A8.21
t
Kw
DIOW negated pulse width min 215 50 25 A8.22
t
Lr
DIOR to DMARQ delay max 120 40 35 A8.23
t
Lw
DIOW to DMARQ delay max 40 40 35 A8.24
WDATA
RDATA
IORDY
t
0
t
1
t
2
t
3
t
4
t
5
t
6
t
9
t
A
t
B
CS[0]/CS[3]/DA[2:0]
DIOR
/DIOW