Datasheet

MPC5200B Data Sheet, Rev. 4
26 Freescale Semiconductor
NOTES:
1. Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified from
0–65535.
2. Example:
Long Burst is used, this means the CS related BERx and SLB bits of the Chip Select Burst Control Register are set and a burst
on the internal XLB is executed. => LB = 1
Data bus width is 8 bit. => DS = 8
=> 4
1
×2×(32/8) = 32 => ACK is asserted for 32 PCI cycles to transfer one cache line.
Wait State is set to 10. => WS = 10
1+10 + 32 = 43 => CS is asserted for 43 PCI cycles.
3. ACK is output and indicates the burst.
4. Deadcycles are only used, if no arbitration to an other module (ATA or PCI) of the shared local bus happens. If arbitration
happens the bus can be driven within 4 IPB clocks by an other modules.
Figure 12. Timing Diagram—Burst Mode
t
9
DATA hold after rising edge of PCI
clock
0 —ns— A7.32
t
10
DATA hold after CS negation 0 (DC + 1) × t
PCIck
ns
(4)
A7.33
t
11
ACK assertion after CS assertion —(WS+1)×t
PCIck
ns — A7.34
t
12
ACK negation before CS negation —7.0ns
(3)
A7.35
t
13
ACK pulse width 4
LB
×2×(32/DS)×t
PCIck
4
LB
×2×(32/DS)×t
PCIck
ns
(2),(3)
A7.36
t
14
CS assertion after TS assertion —2.5ns— A7.37
t
15
TS pulse width t
PCIck
t
PCIck
ns — A7.38
Table 25. Burst Mode Timing (continued)
Sym Description Min Max Units Notes SpecID
ADDR
DATA (rd)
CS[x]
R/W
OE
TS
t
10
t
3
t
5
ACK
t
1
PCI CLK
t
2
t
4
t
7
t
6
t
11
t
13
t
14
t
15
t
9
t
8
t
12