Datasheet

MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor 25
Figure 11. Timing Diagram—Non-MUXed Mode
1.3.8.2 Burst Mode
Table 25. Burst Mode Timing
Sym Description Min Max Units Notes SpecID
t
CSA
PCI CLK to CS assertion 4.6 10.6 ns — A7.22
t
CSN
PCI CLK to CS negation 2.9 7.0 ns — A7.23
t
1
CS pulse width (1 + WS + 4
LB
×2
×(32/DS))×t
PCIck
(1 + WS + 4
LB
×2×
(32/DS)) × t
PCIck
ns
(1),(2)
A7.24
t
2
ADDR valid before CS assertion t
IPBIck
t
PCIck
ns — A7.25
t
3
ADDR hold after CS negation –0.7 —ns— A7.26
t
4
OE assertion before CS assertion —4.8ns— A7.27
t
5
OE negation before CS negation —2.7ns— A7.28
t
6
RW valid before CS assertion t
PCIck
—ns— A7.29
t
7
RW hold after CS negation t
PCIck
—ns— A7.30
t
8
DATA setup before rising edge of
PCI clock
3.6 —ns— A7.31
ADDR
DATA (rd)
CS[x]
R/W
DATA (wr)
OE
t
10
t
11
TS
t
2
t
6
t
8
t
7
t
4
t
3
t
9
TSIZ[1:2]
t
5
t
17
t
16
ACK
t
12
t
13
t
14
t
15
t
1
PCI CLK
t
18
t
19