Datasheet

MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor 23
2. Minimum times are measured at the package pin with the load circuit, and maximum times are measured with the load circuit
as shown in the PCI Local Bus Specification.
3. REQ# and GNT# are point-to-point signals and have different input setup times than do bused signals. GNT# and REQ# have
a setup of 5 ns at 66 MHz. All other signals are bused.
4. See the timing measurement conditions in the PCI Local Bus Specification.
For Measurement and Test Conditions, see the PCI Local Bus Specification.
1.3.8 Local Plus Bus
The Local Plus Bus is the external bus interface of the MPC5200B. A maximum of eight configurable chip selects (CS) are
provided. There are two main modes of operation: non-MUXed (Legacy and Burst) and MUXED. The reference clock is the
PCI CLK. The maximum bus frequency is 66 MHz.
Definition of Acronyms and Terms:
• WS = Wait State
• DC = Dead Cycle
• LB = Long Burst
• DS = Data Size in Bytes
•t
PCIck
= PCI clock period
•t
IPBIck
= IPBI clock period
Figure 10. Timing Diagram—IPBI and PCI clock (example ratio: 4:1)
1.3.8.1 Non-MUXed Mode
Table 24. Non-MUXed Mode Timing
Sym Description Min Max Units Notes SpecID
t
CSA
PCI CLK to CS assertion 4.6 10.6 ns —A7.1
t
CSN
PCI CLK to CS negation 2.9 7.0 ns —A7.2
t
1
CS pulse width (2 + WS) × t
PCIck
(2+WS)×t
PCIck
ns
(1)
A7.3
t
2
ADDR valid before CS assertion t
IPBIck
t
PCIck
ns —A7.4
t
3
ADDR hold after CS negation t
IPBIck
—ns
(2)
A7.5
t
4
OE assertion before CS assertion —4.8ns—A7.6
t
5
OE negation before CS negation —2.7ns—A7.7
t
6
RW valid before CS assertion t
PCIck
—ns—A7.8
t
7
RW hold after CS negation t
IPBIck
—ns—A7.9
t
8
DATA output valid before CS assertion t
IPBIck
—ns— A7.10
t
9
DATA output hold after CS negation t
IPBIck
—ns— A7.11
PCI CLK
IPBI CLK
t
IPBIck
t
PCIck