Datasheet

MPC5200B Data Sheet, Rev. 4
20 Freescale Semiconductor
Figure 7. Timing Diagram—DDR SDRAM Memory Read Timing
MEM_CLK
Control Signals
MDQ (Data)
MA (Address)
MEM_CLK
MDQS (Data Strobe)
NOTE: Control Signals signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN
Active NOP READ NOPNOPNOPNOP NOP
t
hold
Row Column
MBA (Bank Selects)
t
valid
t
hold
t
valid
t
hold
t
valid
t
data_valid_min
t
data_valid_max
Read Data
t
data_sample_min
t
data_sample_max
Sample Window
MDQ (Data)
MDQS (Data Strobe)
t
data_valid_min
t
data_valid_max
Read Data
t
data_sample_min
t
data_sample_max
Sample Window
Sample position A: data are sampled on the expected edge of MEM_CLK, the MDQS signal indicate the valid data
Sample
position
A
Sample
position
B
Sample position B: data are sampled on a later edge of MEM_CLK, SDRAM controller is waiting for the valid MDQS signal
0.5
× t
MEM_CLK