Datasheet

MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor 19
Figure 6. Timing Diagram—Standard SDRAM Memory Write Timing
1.3.6.3 Memory Interface Timing-DDR SDRAM Read Command
The SDRAM Memory Controller uses a 1/4 period delayed MDQS strobe to capture the MDQ data. The 1/4 period delay value
is calculated automatically by hardware.
Table 20. DDR SDRAM Memory Read Timing
Sym Description Min Max Units SpecID
t
mem_clk
MEM_CLK period 7.5 — ns A5.15
t
valid
Control Signals, Address and MBA
valid after rising edge of MEM_CLK
—t
mem_clk
×0.5+0.4 ns A5.16
t
hold
Control Signals, Address and MBA
hold after rising edge of MEM_CLK
t
mem_clk
× 0.5 — ns A5.17
data
setup
Setup time relative to MDQS — 0.4 ns A5.18
data
hold
Hold time relative to MDQS 2.6 — ns A5.19
MEM_CLK
Control Signals
MDQ (Data)
MA (Address)
NOTE: Control Signals are composed of RAS, CAS, MEM_WE
, MEM_CS, MEM_CS1 and CLK_EN
Active NOP WRITE NOPNOPNOPNOP NOP
t
hold
Row Column
MBA (Bank Selects)
data
hold
data
valid
t
valid
t
hold
t
valid
t
hold
t
valid
DQM (Data Mask)
DM
valid
DM
hold