Datasheet

MPC5200B Data Sheet, Rev. 4
18 Freescale Semiconductor
Figure 5. Timing Diagram—Standard SDRAM Memory Read Timing
1.3.6.2 Memory Interface Timing-Standard SDRAM Write Command
In Standard SDRAM, all signals are activated on the MEM_CLK from the Memory Controller and captured on the MEM_CLK
clock at the memory device.
Table 19. Standard SDRAM Write Timing
Sym Description Min Max Units SpecID
t
mem_clk
MEM_CLK period 7.5 — ns A5.8
t
valid
Control Signals, Address and MBA Valid
after rising edge of MEM_CLK
—t
mem_clk
× 0.5 + 0.4 ns A5.9
t
hold
Control Signals, Address and MBA Hold after
rising edge of MEM_CLK
t
mem_clk
× 0.5 — ns A5.10
DM
valid
DQM valid after rising edge of MEM_CLK — t
mem_clk
× 0.25 + 0.4 ns A5.11
DM
hold
DQM hold after rising edge of Mem_clk t
mem_clk
×0.25–0.7 — ns A5.12
data
valid
MDQ valid after rising edge of MEM_CLK — t
mem_clk
× 0.75 + 0.4 ns A5.13
data
hold
MDQ hold after rising edge of MEM_CLK t
mem_clk
×0.75–0.7 — ns A5.14
MEM_CLK
Control Signals
MDQ (Data)
MA (Address)
NOTE: Control Signals are composed of RAS, CAS, MEM_WE
, MEM_CS, MEM_CS1 and CLK_EN
Active NOP READ NOPNOPNOP NOP
t
hold
Row Column
MBA (Bank Selects)
t
valid
t
hold
t
valid
t
hold
t
valid
DQM (Data Mask)
DM
valid
DM
hold
NOP
data
hold
data
setup