Datasheet

MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor 13
• Input conditions:
All Inputs: tr, tf <= 1 ns
• Output Loading:
All Outputs: 50 pF
1.3.2 AC Operating Frequency Data
Table 12 provides the operating frequency information for the MPC5200B.
1.3.3 Clock AC Specifications
Figure 2. Timing Diagram—SYS_XTAL_IN
Table 12. Clock Frequencies
Min Max Units SpecID
1 e300 Processor Core — 400 MHz A1.1
2 SDRAM Clock — 133 MHz A1.2
3 XL Bus Clock — 133 MHz A1.3
4 IP Bus Clock — 133 MHz A1.4
5 PCI / Local Plus Bus Clock — 66 MHz A1.5
6 PLL Input Range 15.6 35 MHz A1.6
Table 13. SYS_XTAL_IN Timing
Sym Description Min Max Units SpecID
t
CYCLE
SYS_XTAL_IN cycle time.
(1)
1
CAUTION—The SYS_XTAL_IN frequency and system PLL_CFG[0–6] settings must be chosen such that the resulting
system frequencies do not exceed their respective maximum or minimum operating frequencies. See the MPC5200B
User’s Manual (MPC5200BUM).
28.6 64.1 ns A2.1
t
RISE
SYS_XTAL_IN rise time. — 5.0 ns A2.2
t
FALL
SYS_XTAL_IN fall time. — 5.0 ns A2.3
t
DUTY
SYS_XTAL_IN duty cycle (measured at V
M
).
(2)
2
SYS_XTAL_IN duty cycle is measured at V
M
.
40.0 60.0 % A2.4
CV
IH
SYS_XTAL_IN input voltage high 2.0 — V A2.5
CV
IL
SYS_XTAL_IN input voltage low — 0.8 V A2.6
t
FALL
t
RISE
t
CYCLE
SYSCLK
t
DUTY
t
DUTY
CV
IH
CV
IL
V
M
V
M
V
M