Datasheet

MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor 11
1.2.1 System Oscillator Electrical Characteristics
1.2.2 RTC Oscillator Electrical Characteristics
1.2.3 System PLL Electrical Characteristics
1.2.4 e300 Core PLL Electrical Characteristics
The internal clocking of the e300 core is generated from and synchronized to the system clock by means of a voltage-controlled
core PLL.
Table 8. System Oscillator Electrical Characteristics
Characteristic Sym Notes Min Typical Max Unit SpecID
SYS_XTAL frequency f
sys_xtal
15.6 33.3 35.0 MHz O1.1
Oscillator start-up time t
up_osc
— — 10 ms O1.2
Table 9. RTC Oscillator Electrical Characteristics
Characteristic Sym Notes Min Typical Max Unit SpecID
RTC_XTAL frequency f
rtc_xtal
— 32.768 — kHz O2.1
Table 10. System PLL Specifications
Characteristic Sym Notes Min Typical Max Unit SpecID
SYS_XTAL frequency f
sys_xtal
(1)
1
The SYS_XTAL frequency and PLL Configuration bits must be chosen such that the resulting system frequency, CPU
(core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies.
15.6 33.3 35.0 MHz O3.1
SYS_XTAL cycle time t
sys_xtal
(1)
66.6 30.0 28.5 ns O3.2
SYS_XTAL clock input jitter t
jitter
(2)
2
This represents total input jitter—short term and long term combined—and is guaranteed by design. Two different
types of jitter can exist on the input to CORE_SYSCLK, systemic and true random jitter. True random jitter is rejected.
Systemic jitter is passed into and through the PLL to the internal clock circuitry.
— — 150 ps O3.3
System VCO frequency f
VCOsys
(1) 250 533 800 MHz O3.4
System PLL relock time t
lock
(3)
3
Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required
for the PLL lock after a stable VDD and CORE_SYSCLKare reached during the power-on reset sequence. This
specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.
— — 100 μsO3.5