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Freescale Semiconductor

Data Sheet: Technical Data

Document Number: MPC5200BDS

Rev. 4, 02/2010

Freescale reserves the right to change the detail specifications as may be required to permit

improvements in the design of its products.

TEPBGA–272

27 mm x 27 mm

Key features are shown below.

• MPC603e series e300 core

– Superscalar architecture

– 760 MIPS at 400 MHz (–40

C to +85

– 16 KB Instruction cache, 16 KB Data cache

– Double precision FPU

– Instruction and Data MMU

– Standard and Critical interrupt capability

• SDRAM / DDR Memory Interface

– Up to 133 MHz operation

– SDRAM and DDR SDRAM support

– 256 MB addressing range per CS, two CS available

– 32-bit data bus

– Built-in initialization and refresh

• Flexible multi-function External Bus Interface

– Supports interfacing to ROM/Flash/SRAM memories or

other memory mapped devices

– 8 programmable Chip Selects

– Non-multiplexed data access using 8-/16-/32-bit databus

with up to 26-bit address

– Short or Long Burst capable

– Multiplexed data access using 8-/16-/32-bit databus

with up to 25-bit address

• Peripheral Component Interconnect (PCI) Controller

– Version 2.2 PCI compatibility

– PCI initiator and target operation

– 32-bit PCI Address/Data bus

– 33 and 66 MHz operation

– PCI arbitration function

• ATA Controller

– Version 4 ATA compatible external interface—IDE Disk

Drive connectivity

• BestComm DMA subsystem

– Intelligent virtual DMA Controller

– Dedicated DMA channels to control peripheral

reception and transmission

– Local memory (SRAM 16 KB)

• 6 Programmable Serial Controllers (PSC)

– UART or RS232 interface

– CODEC interface for Soft Modem, Master/Slave

CODEC Mode, I

S and AC97

– Full duplex SPI mode

– IrDA mode from 2400 bps to 4 Mbps

• Fast Ethernet Controller (FEC)

– Supports 100Mbps IEEE 802.3 MII, 10 Mbps IEEE

802.3 MII, 10 Mbps 7-wire interface

• Universal Serial Bus Controller (USB)

– USB Revision 1.1 Host

– Open Host Controller Interface (OHCI)

– Integrated USB Hub, with two ports.

• Two Inter-Integrated Circuit Interfaces (I

• Serial Peripheral Interface (SPI)

• Dual CAN 2.0 A/B Controller (MSCAN)

– Implementation of version 2.0A/B CAN protocol

– Standard and extended data frames

• J1850 Byte Data Link Controller (BDLC)

• J1850 Class B data communication network interface

compatible and ISO compatible for low speed (<125 kbps)

serial data communications in automotive applications.

• Supports 4X mode, 41.6 kbps

• In-frame response (IFR) types 0, 1, 2, and 3 supported

• Systems level features

– Interrupt Controller supports four external interrupt

request lines and 47 internal interrupt sources

– GPIO/Timer functions

Up to 56 total GPIO pins that support a variety of

interrupt/WakeUp capabilities.

Eight GPIO pins with timer capability supporting input

capture, output compare, and pulse width modulation

(PWM) functions

– Real-time Clock with one-second resolution

– Systems Protection (watch dog timer, bus monitor)

– Individual control of functional block clock sources

– Power management: Nap, Doze, Sleep, Deep Sleep

modes

– Support of WakeUp from low power modes by different

sources (GPIO, RTC, CAN)

• Test/Debug features

– JTAG (IEEE 1149.1 test access port)

– Common On-chip Processor (COP) debug port

• On-board PLL and clock generation

MPC5200B Data Sheet

Summary of content (72 pages)

PAGE 1
Freescale Semiconductor Data Sheet: Technical Data Document Number: MPC5200BDS Rev. 4, 02/2010 MPC5200B Data Sheet Key features are shown below.
PAGE 2
Table of Contents 1 Electrical and Thermal Characteristics . . . . . . . . . . . . . . . . . . .4 1.1 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . .4 1.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . .4 1.1.2 Recommended Operating Conditions . . . . . . . . .4 1.1.3 DC Electrical Specifications. . . . . . . . . . . . . . . . .5 1.1.4 Electrostatic Discharge . . . . . . . . . . . . . . . . . . . .7 1.1.5 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
Freescale Semiconductor Figure 1 shows a simplified MPC5200B block diagram. SDRAM/DDR Systems Interface Unit (SIU) Real-Time Clock SDRAM/DDR Memory Controller System Functions 603 e300 Core Interrupt Controller GPIO/Timers MPC5200B Data Sheet, Rev. 4 Local Plus Controller JTAG / COP Interface Local Bus SRAM 16 KB Reset / Clock Generation BestComm DMA PCI Bus Controller ATA Host Controller CommBus PSC 6x Ethernet I2C 2x SPI USB 2x Figure 1.
PAGE 4
1 Electrical and Thermal Characteristics 1.1 DC Electrical Characteristics 1.1.1 Absolute Maximum Ratings The tables in this section describe the MPC5200B DC Electrical characteristics. Table 1 gives the absolute maximum ratings. Table 1. Absolute Maximum Ratings(1) Characteristic Sym Min Max Unit SpecID Supply voltage — e300 core and peripheral logic VDD_CORE –0.3 1.8 V D1.1 VDD_IO, VDD_MEM_IO –0.3 3.6 V D1.2 SYS_PLL_AVDD –0.3 2.1 V D1.3 CORE_PLL_AVDD –0.3 2.1 V D1.
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Table 2. Recommended Operating Conditions (continued) Sym Min(1) Max(1) Unit SpecID Vin 0 VDD_IO V D2.7 Input voltage — memory I/O buffers (SDR) VinSDR 0 VDD_MEM_IOSDR V D2.8 Input voltage — memory I/O buffers (DDR) VinDDR 0 VDD_MEM_IODDR V D2.9 TA –40 +85 o C D2.10 +115 o C D2.
PAGE 6
Table 3. DC Electrical Specifications (continued) Characteristic Condition Sym Min Max Unit SpecID Input leakage current RTC_XTAL_IN Vin = 0 or VDD_IO IIN — ±10 μA D3.15 Input current, pullup resistor PULLUP VDD_IO Vin = 0 IINpu 40 109 μA D3.16 Input current, pullup resistor — memory I/O buffers PULLUP_MEM VDD_IO_MEMSDR Vin = 0 IINpu 41 111 μA D3.17 Input current, pulldown resistor PULLDOWN VDD_IO Vin = VDD_IO IINpd 36 106 μA D3.
PAGE 7
1.1.4 Electrostatic Discharge CAUTION This device contains circuitry that protects against damage due to high-static voltage or electrical fields. However, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages. Operational reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (GND or VCC ). Table 7 gives package thermal characteristics for this device. Table 5.
PAGE 8
Table 6. Power Dissipation Core Power Supply (VDD_CORE) SYS_XTAL/XLB/PCI/IPB/CORE (MHz) SpecID Mode 33/66/33/33/264 33/132/66/132/396 Typ Typ Operational 727.5 Doze Nap Sleep Deep-Sleep Unit Notes 1080 mW (1),(2) D5.1 — 600 mW (1),(3) D5.2 — 225 mW (1),(4) D5.3 mW (1),(5) D5.4 mW (1),(6) D5.5 — 225 52.5 52.5 PLL Power Supplies (SYS_PLL_AVDD, CORE_PLL_AVDD) Mode Typ Unit Notes Typical 2 mW (7) D5.
PAGE 9
1.1.6 Thermal Characteristics Table 7. Thermal Resistance Data Rating Board Layers Sym Value Unit Notes SpecID RθJA 30 °C/W (1),(2) D6.1 Junction to Ambient Natural Convection Single layer board (1s) Junction to Ambient Natural Convection Four layer board (2s2p) RθJMA 22 °C/W (1),(3) D6.2 Junction to Ambient (@200 ft/min) Single layer board (1s) RθJMA 24 °C/W (1),(3) D6.3 Junction to Ambient (@200 ft/min) Four layer board (2s2p) RθJMA 19 °C/W (1),(3) D6.
PAGE 10
R θJA = R θJC +R θCA Eqn. 4 where: R θJA = junction to ambient thermal resistance (ºC/W) R θJC = junction to case thermal resistance (ºC/W) R θCA = case to ambient thermal resistance (ºC/W) R θJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, R θCA.
PAGE 11
1.2.1 System Oscillator Electrical Characteristics Table 8. System Oscillator Electrical Characteristics 1.2.2 Characteristic Sym SYS_XTAL frequency Oscillator start-up time Notes Min Typical Max Unit SpecID fsys_xtal 15.6 33.3 35.0 MHz O1.1 tup_osc — — 10 ms O1.2 RTC Oscillator Electrical Characteristics Table 9. RTC Oscillator Electrical Characteristics 1.2.3 Characteristic Sym RTC_XTAL frequency frtc_xtal Notes Min Typical Max Unit SpecID — 32.768 — kHz O2.
PAGE 12
Table 11. e300 PLL Specifications Characteristic Sym Notes Min Typical Max Unit SpecID e300 frequency fcore (1) 50 — 550 MHz O4.1 e300 cycle time tcore (1) 2.85 — 40.0 ns O4.2 e300 VCO frequency fVCOcore (1) 400 — 1200 MHz O4.3 e300 input clock frequency fXLB_CLK — 25 — 367 MHz O4.4 e300 input clock cycle time tXLB_CLK — 2.73 — 50.0 ns O4.5 e300 input clock jitter tjitter (2) — — 150 ps O4.6 tlock (3) — — 100 μs O4.
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• • Input conditions: All Inputs: tr, tf <= 1 ns Output Loading: All Outputs: 50 pF 1.3.2 AC Operating Frequency Data Table 12 provides the operating frequency information for the MPC5200B. Table 12. Clock Frequencies Min Max Units SpecID 1 e300 Processor Core — 400 MHz A1.1 2 SDRAM Clock — 133 MHz A1.2 3 XL Bus Clock — 133 MHz A1.3 4 IP Bus Clock — 133 MHz A1.4 5 PCI / Local Plus Bus Clock — 66 MHz A1.5 6 PLL Input Range 15.6 35 MHz A1.6 1.3.
PAGE 14
1.3.4 Resets The MPC5200B has three reset pins: • • • PORRESET—Power on Reset HRESET—Hard Reset SRESET—Software Reset These signals are asynchronous I/O signals and can be asserted at any time. The input side uses a Schmitt trigger and requires the same input characteristics as other MPC5200B inputs, as specified in the DC Electrical Specifications section. Table 14 specifies the pulse widths of the Reset inputs. Table 14.
PAGE 15
For additional information, see the MPC5200B User’s Manual (MPC5200BUM). 1.3.4.1 Reset Configuration Word During reset (HRESET and PORRESET) the Reset Configuration Word is latched in the related Reset Configuration Word Register with each rising edge of the SYS_XTAL signal. If both resets (HRESET and PORRESET) are inactive (high), the contents of this register are locked immediately with the SYS_XTAL clock (see Figure 3).
PAGE 16
IRQ0 cint CORE_CINT Encoder 8 GPIOs 8 CORE_INT GPIO Std int 8 GPIOs 8 GPIO WakeUp e300 Core Grouper Encoder IRQ1 IRQ2 PIs Main Interrupt Controller IRQ3 Notes: 1. PIs = Programmable Inputs 2. Grouper and Encoder functions imply programmability in software Figure 4. External Interrupt Scheme Due to synchronization, prioritization, and mapping of external interrupt sources, the propagation of external interrupts to the core processor is delayed by several IP_CLK clock cycles.
PAGE 17
2) The interrupt latency descriptions in the table above are related to non competitive, non masked but enabled external interrupt sources. Take care of interrupt prioritization which may increase the latencies. Because all external interrupt signals are synchronized into the internal processor bus clock domain, each of these signals has to exceed a minimum pulse width of more than one IP_CLK cycle. Table 17.
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MEM_CLK tvalid thold Active Control Signals NOP READ DMvalid NOP NOP NOP NOP NOP DMhold DQM (Data Mask) datasetup datahold MDQ (Data) tvalid thold Row MA (Address) Column tvalid thold MBA (Bank Selects) NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN Figure 5. Timing Diagram—Standard SDRAM Memory Read Timing 1.3.6.
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MEM_CLK tvalid thold Active Control Signals NOP WRITE NOP NOP NOP NOP NOP DMhold DMvalid DQM (Data Mask) datavalid datahold MDQ (Data) tvalid thold Row MA (Address) tvalid Column thold MBA (Bank Selects) NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN Figure 6. Timing Diagram—Standard SDRAM Memory Write Timing 1.3.6.
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MEM_CLK MEM_CLK tvalid thold Active Control Signals NOP READ NOP NOP NOP NOP NOP MDQS (Data Strobe) tdata_valid_min tdata_valid_max MDQ (Data) Sample position A tdata_sample_min tdata_sample_max Read Data Sample Window MDQS (Data Strobe) tdata_valid_min tdata_valid_max MDQ (Data) 0.
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1.3.6.4 Memory Interface Timing-DDR SDRAM Write Command Table 21. DDR SDRAM Memory Write Timing Sym Description Min Max Units SpecID tmem_clk MEM_CLK period 7.5 — ns A5.20 tDQSS Delay from write command to first rising edge of MDQS — tmem_clk + 0.4 ns A5.21 datavalid MDQ valid before rising edge of MDQS 1.0 — ns A5.22 datahold MDQ valid after rising edge of MDQS 1.0 — ns A5.
PAGE 22
t cyc t high t low 0.6 Vcc 0.5 Vcc 0.4 Vcc PCI CLK 0.3 Vcc 0.4 Vcc, p-to-p (minimum) 0.2 Vcc Figure 9. PCI CLK Waveform Table 22. PCI CLK Specifications 66 MHz Sym 33 MHz Description Min Max Min Max Units Notes SpecID tcyc PCI CLK Cycle Time 15 30 30 — ns (1),(3) A6.1 thigh PCI CLK High Time 6 — 11 — ns — A6.2 t low PCI CLK Low Time 6 — 11 — ns — A6.3 — PCI CLK Slew Rate 1.5 4 1 4 V/ns (2) A6.
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2. Minimum times are measured at the package pin with the load circuit, and maximum times are measured with the load circuit as shown in the PCI Local Bus Specification. 3. REQ# and GNT# are point-to-point signals and have different input setup times than do bused signals. GNT# and REQ# have a setup of 5 ns at 66 MHz. All other signals are bused. 4. See the timing measurement conditions in the PCI Local Bus Specification. For Measurement and Test Conditions, see the PCI Local Bus Specification. 1.3.
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Table 24. Non-MUXed Mode Timing (continued) Sym Description Min Max Units t10 DATA input setup before CS negation 8.5 — ns — A7.12 ns (6) A7.13 A7.14 t11 DATA input hold after CS negation 0 (DC + 1) × tPCIck Notes SpecID t12 ACK assertion after CS assertion tPCIck — ns (3) t13 ACK negation after CS negation — tPCIck ns (3) A7.15 ns (4) A7.16 ns (4) A7.17 A7.18 t14 t15 TS assertion before CS assertion TS pulse width — tPCIck 6.
PAGE 25
PCI CLK t1 CS[x] t2 t3 ADDR t5 t4 OE t6 t7 R/W t8 t9 DATA (wr) t10 t11 DATA (rd) t19 t12 ACK t14 t13 t18 t15 TS t17 TSIZ[1:2] t16 Figure 11. Timing Diagram—Non-MUXed Mode 1.3.8.2 Burst Mode Table 25. Burst Mode Timing Sym Description Min Max t CSA PCI CLK to CS assertion 4.6 10.6 ns t CSN PCI CLK to CS negation 2.9 7.0 4LB 4LB Units Notes SpecID — A7.22 ns — A7.23 A7.
PAGE 26
Table 25. Burst Mode Timing (continued) Sym Description Min Max Units Notes SpecID t9 DATA hold after rising edge of PCI clock 0 — ns — A7.32 t10 DATA hold after CS negation 0 (DC + 1) × tPCIck ns (4) A7.33 t11 ACK assertion after CS assertion — (WS + 1) × tPCIck ns — A7.34 t12 ACK negation before CS negation — 7.0 ns (3) A7.35 t13 ACK pulse width ns (2),(3) A7.36 t14 CS assertion after TS assertion — 2.5 ns — A7.37 t15 TS pulse width tPCIck tPCIck ns — A7.
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1.3.8.3 MUXed Mode Table 26. MUXed Mode Timing Sym Description Min Max Units Notes SpecID t CSA PCI CLK to CS assertion 4.6 10.6 ns — A7.39 t CSN PCI CLK to CS negation 2.9 7.0 ns — A7.40 tALEA PCI CLK to ALE assertion — 3.6 ns — A7.41 t1 ALE assertion before Address, Bank, TSIZ assertion — 5.7 ns — A7.42 t2 CS assertion before Address, Bank, TSIZ negation — –1.2 ns — A7.43 t3 CS assertion before Data wr valid — –1.2 ns — A7.
PAGE 28
PCI CLK t2 t1 t4 AD[31,27] (wr) Data AD[30:28] (wr) TSIZ[0:2] bits Data AD[26:25] (wr) Bank[0:1] bits Data AD[24:0] (wr) Address[7:31] Data t3 t5 AD[31:0] (rd) t6 Data t7 t14 ALE t8 Address latch TS t9 CSx OE t10 t11 R/W t16 t12 ACK t15 Address tenure t13 Data tenure Figure 13. Timing Diagram—MUXed Mode 1.3.9 ATA The MPC5200B ATA Controller is completely software programmable.
PAGE 29
All ATA transfers are programmed in terms of system clock cycles (IP bus clocks) in the ATA Host Controller timing registers. This puts constraints on the ATA protocols and their respective timing modes in which the ATA Controller can communicate with the drive. Faster ATA modes (i.e., UDMA 0, 1, 2) are supported when the system is running at a sufficient frequency to provide adequate data transfer rates.
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CS[0]/CS[3]/DA[2:0] t2 DIOR/DIOW t9 t1 t0 t3 t4 WDATA t5 t6 RDATA tA tB IORDY Figure 14. PIO Mode Timing Table 28. Multiword DMA Timing Specifications Sym Multiword DMA Timing Parameters Min/Max Mode 0(ns) Mode 1(ns) Mode 2(ns) SpecID t0 Cycle Time min 480 150 120 A8.12 tC DMACK to DMARQ delay max — — — A8.13 tD DIOR/DIOW pulse width (16-bit) min 215 80 70 A8.14 tE DIOR data access max 150 60 50 A8.15 tG DIOR/DIOW data setup min 100 30 20 A8.
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t0 DMARQ (Drive) tL tC DMACK (Host) tD tI tJ tK DIOR DIOW (Host) tE RDATA (Drive) tF WDATA (Host) tG tH Figure 15. Multiword DMA Timing NOTE The direction of signal assertion is towards the top of the page, and the direction of negation is towards the bottom of the page, irrespective of the electrical properties of the signal. Table 29.
PAGE 32
Table 29. Ultra DMA Timing Specification (continued) Sym MODE 0 (ns) MODE 1 (ns) MODE 2 (ns) Comment SpecID Min Max Min Max Min Max t AZ — 10 — 10 — 10 Maximum time allowed for output drivers to release from being asserted or negated A8.36 t ZAH 20 — 20 — 20 — A8.
PAGE 33
DMARQ (device) t UI DMACK (device) t ACK t ENV t FS t ZAD STOP (host) t ACK t ENV t FS HDMARDY (host) t ZAD t ZIORDY DSTROBE (device) t DVS t AZ t DVH DD(0:15) t ACK DA0, DA1, DA2, CS[0:1]1 Figure 16. Timing Diagram—Initiating an Ultra DMA Data In Burst t 2CYC t CYC t CYC t 2CYC DSTROBE at device tDVH tDVS tDVH tDVS tDVH DD(0:15) at device DSTROBE at host tDH tDS tDH tDS tDH DD(0:15) at host Figure 17. Timing Diagram—Sustained Ultra DMA Data In Burst MPC5200B Data Sheet, Rev.
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DMARQ (device) DMARQ (host) t RP STOP (host) t SR HDMARDY (host) t RFS DSTROBE (device) DD[0:15] (device) Figure 18. Timing Diagram—Host Pausing an Ultra DMA Data In Burst DMARQ (device) DMACK (host) t LI t MLI t LI t ACK STOP (host) tLI t ACK HDMARDY (host) t SS t IORDYZ DSTROBE (device) t ZAH t DVS t AZ t DVH CRC DD[0:15] t ACK DA0,DA1,DA2, CS[0:1] Figure 19. Timing Diagram—Drive Terminating Ultra DMA Data In Burst MPC5200B Data Sheet, Rev.
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DMARQ (device) t LI t MLI DMACK (host) t RP t ZAH t ACK STOP (host) tACK t AZ HDMARDY (host) t RFS t MLI t LI DSTROBE (device) t IORDYZ t DVS t DVH DD[0:15] CRC t ACK DA0,DA1,DA2, CS[0:1] Figure 20. Timing Diagram—Host Terminating Ultra DMA Data In Burst DMARQ (device) tUI DMACK (host) tACK tENV STOP (host) tLI tZIORDY tUI DDMARDY (host) tACK HSTROBE (device) tDVS tDVH DD[0:15] (host) tACK DA0,DA1,DA2, CS[0:1] Figure 21.
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t 2CYC t CYC t CYC t 2CYC HSTROBE (host) t DVS t DVH t DVS t DVH t DVH DD[0:15] (host) HSTROBE (device) t DH t DS t DS t DH t DH DD[0:15] (device) Figure 22. Timing Diagram—Sustained Ultra DMA Data Out Burst t RP DMARQ (device) DMACK (host) STOP (host) t SR DDMARDY (device) t RFS HSTROBE DD[0:15] (host) Figure 23. Timing Diagram—Drive Pausing an Ultra DMA Data Out Burst MPC5200B Data Sheet, Rev.
PAGE 37
DMARQ (device) t LI t MLI DMACK (host) t SS t ACK t LI STOP (host) t LI t IORDYZ DDMARDY (device) tACK HSTROBE (host) t DVS DD[0:15] (host) t DVH CRC t ACK DA0,DA1,DA2, CS[0:1] Figure 24. Timing Diagram—Host Terminating Ultra DMA Data Out Burst DMARQ (device) DMACK (host) t LI t MLI t ACK STOP (host) t RP t IORDYZ DDMARDY (device) t RFS t LI t MLI t ACK HSTROBE (host) t DVS DD[0:15] (host) t DVH CRC t ACK DA0,DA1,DA2, CS[0:1] Figure 25.
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Table 30. Timing Specification ata_isolation Sym Description Min Max Units SpecID 1 ata_isolation setup time 7 — IP Bus cycles A8.48 2 ata_isolation hold time — 19 IP Bus cycles A8.49 DIOR ATA_ISOLATION 1 2 Figure 26. Timing Diagram—ATA-ISOLATION 1.3.10 Ethernet AC Test Timing Conditions: • Output Loading All Outputs: 25 pF Table 31. MII Rx Signal Timing Sym Description Min Max Unit SpecID t1 RXD[3:0], RX_DV, RX_ER to RX_CLK setup 10 — ns A9.
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Table 32. MII Tx Signal Timing Sym Description Min Max Unit SpecID t5 TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER invalid 5 — ns A9.5 t6 TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER valid — 25 ns A9.6 t7 TX_CLK pulse width high 35% 65% TX_CLK Period(1) A9.7 65% (1) A9.8 TX_CLK pulse width low t8 1 35% TX_CLK Period The TX_CLK frequency shall be 25% of the nominal transmit frequency, e.g.
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Table 34. MII Serial Management Channel Signal Timing Sym Description Min Max Unit SpecID t10 MDC falling edge to MDIO output delay 0 25 ns A9.10 t11 MDIO (input) to MDC rising edge setup 10 — ns A9.11 t12 MDIO (input) to MDC rising edge hold 10 — ns A9.12 160 — ns A9.13 t13 MDC pulse width high (1) t14 MDC pulse width low(1) 160 — ns A9.14 t15 MDC period(2) 400 — ns A9.
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2 USB_OE 4 3 USB_TXN 1 1 3 4 USB_TXP Figure 31. Timing Diagram—USB Output Line 1.3.12 SPI Table 36. Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0) 1 Sym Description Min Max Units SpecID 1 Cycle time 4 1024 IP-Bus Cycle(1) A11.1 Cycle(1) A11.2 2 Clock high or low time 2 512 IP-Bus 3 Slave select to clock delay 15.0 — ns A11.3 4 Output Data valid after Slave Select (SS) — 20.0 ns A11.4 5 Output Data valid after SCK — 20.0 ns A11.
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1 10 SCK (CLKPOL=0) Output 2 2 11 SCK (CLKPOL=1) Output 11 10 9 8 3 SS Output 5 4 MOSI Output 6 6 MISO Input 7 7 Figure 32. Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0) Table 37. Timing Specifications — SPI Slave Mode, Format 0 (CPHA = 0) Sym Description Min Max Units 1 Cycle time 4 1024 IP-Bus Cycle(1) A11.12 (1) A11.13 2 Clock high or low time 2 512 3 Slave select to clock delay 15.0 — ns A11.14 4 Output Data valid after Slave Select (SS) — 50.0 ns A11.
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1 SCK (CLKPOL=0) Input 2 2 SCK (CLKPOL=1) Input 8 3 9 SS Input 6 7 MOSI Input 4 5 MISO Output Figure 33. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0) Table 38. Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1) 1 Sym Description Min Max Units SpecID 1 Cycle time 4 1024 IP-Bus Cycle(1) A11.21 2 Clock high or low time 2 512 IP-Bus Cycle(1) A11.22 3 Slave select to clock delay 15.0 — ns A11.23 4 Output data valid — 20.0 ns A11.
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1 9 SCK (CLKPOL=0) Output 2 2 10 SCK (CLKPOL=1) Output 10 9 7 3 8 SS Output 4 MOSI Output 5 MISO Input 6 Figure 34. Timing Diagram — SPI Master Mode, Format 1 (CPHA = 1) Table 39. Timing Specifications — SPI Slave Mode, Format 1 (CPHA = 1) 1 Sym Description Min Max Units SpecID 1 Cycle time 4 1024 IP-Bus Cycle(1) A11.31 2 Clock high or low time 2 512 IP-Bus Cycle(1) A11.32 3 Slave select to clock delay 15.0 — ns A11.33 4 Output data valid — 50.0 ns A11.
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1 SCK (CLKPOL=0) Input 2 2 SCK (CLKPOL=1) Input 8 7 3 SS Input 5 6 MOSI Input 4 MISO Output Figure 35. Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1) 1.3.13 MSCAN The CAN functions are available as RX and TX pins at normal IO pads (I2C1+GPTimer or PSC2). There is no filter for the WakeUp dominant pulse. Any High-to-Low edge can cause WakeUp, if configured. 1.3.14 I2C Table 40.
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Table 41. I2C Output Timing Specifications—SCL and SDA Sym Description Min (1) Start condition hold time 6 2(1) Clock low time (2) SCL/SDA rise time 1 3 4 (1) Max Units SpecID — IP-Bus Cycle(3) A13.8 10 — IP-Bus Cycle(3) A13.9 — 7.9 ns A13.10 (3) Data hold time 7 — IP-Bus Cycle 5(1) SCL/SDA fall time — 7.9 6(1) Clock high time 10 — IP-Bus Cycle(3) A13.13 7(1) Data setup time 2 — IP-Bus Cycle(3) A13.
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1.3.16 PSC 1.3.16.1 Codec Mode (8-,16-, 24-, and 32-bit)/I2S Mode Table 42. Timing Specifications—8-, 16-, 24-, and 32-bit CODEC / I2S Master Mode 1 Sym Description Min Typ Max Units SpecID 1 Bit Clock cycle time, programmed in CCS register 40.0 — — ns A15.1 (1) 2 Clock duty cycle — 50 — % A15.2 3 Bit Clock fall time — — 7.9 ns A15.3 4 Bit Clock rise time — — 7.9 ns A15.4 5 FrameSync valid after clock edge — — 8.4 ns A15.
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Table 43. Timing Specifications — 8-, 16-, 24-, and 32-bit CODEC / I2S Slave Mode 1 Sym Description Min Typ Max Units SpecID 1 Bit Clock cycle time 40.0 — — ns A15.9 2 Clock duty cycle — 50 — %(1) A15.10 3 FrameSync setup time 1.0 — — ns A15.11 4 Output Data valid after clock edge — — 14.0 ns A15.12 5 Input Data setup time 1.0 — — ns A15.13 6 Input Data hold time 1.0 — — ns A15.14 Bit Clock cycle time.
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1.3.16.2 AC97 Mode Table 44. Timing Specifications — AC97 Mode Sym Description Min Typ Max Units SpecID 1 Bit Clock cycle time — 81.4 — ns A15.15 2 Clock pulse high time — 40.7 — ns A15.16 3 Clock pulse low time — 40.7 — ns A15.17 4 FrameSync valid after rising clock edge — — 13.0 ns A15.18 5 Output Data valid after rising clock edge — — 14.0 ns A15.19 6 Input Data setup time 1.0 — — ns A15.20 7 Input Data hold time 1.0 — — ns A15.
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3 IrDA_TX (SIR / FIR / MIR) 4 1 2 Figure 40. Timing Diagram — IrDA Transmit Line 1.3.16.4 SPI Mode Table 46. Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0) Sym Description Min Max Units SpecID 1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A15.26 2 SCK pulse width, 50% SCK duty cycle 15.0 — ns A15.27 3 Slave select clock delay, programable in the PSC CCS register 30.0 — ns A15.28 4 Output Data valid after Slave Select (SS) — 8.9 ns A15.
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1 10 SCK (CLKPOL=0) Output 2 2 11 SCK (CLKPOL=1) Output 11 10 9 8 3 SS Output 5 4 MOSI Output 6 6 MISO Input 7 7 Figure 41. Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0) Table 47. Timing Specifications — SPI Slave Mode, Format 0 (CPHA = 0) Sym Description Min Max Units SpecID 1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A15.37 2 SCK pulse width, 50% SCK duty cycle 15.0 — ns A15.38 3 Slave select clock delay 1.0 — ns A15.
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1 SCK (CLKPOL=0) Input 2 2 SCK (CLKPOL=1) Input 9 8 3 SS Input 5 4 MOSI Input 6 7 MISO Output Figure 42. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0) Table 48. Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1) Sym Description Min Max Units SpecID 1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A15.46 2 SCK pulse width, 50% SCK duty cycle 15.0 — ns A15.47 3 Slave select clock delay, programable in the PSC CCS register 30.0 — ns A15.
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1 9 SCK (CLKPOL=0) Output 2 2 10 SCK (CLKPOL=1) Output 10 9 8 7 3 SS Output 4 MOSI Output 5 MISO Input 6 Figure 43. Timing Diagram — SPI Master Mode, Format 1 (CPHA = 1) Table 49. Timing Specifications — SPI Slave Mode, Format 1 (CPHA = 1) Sym Description Min Max Units SpecID 1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A15.56 2 SCK pulse width, 50% SCK duty cycle 15.0 — ns A15.57 3 Slave select clock delay 0.0 — ns A15.58 4 Output data valid — 14.
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1 SCK (CLKPOL=0) Input 2 2 SCK (CLKPOL=1) Input 7 3 8 SS Input 5 6 MOSI Input 4 MISO Output Figure 44. Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1) 1.3.17 1.3.17.1 GPIOs and Timers General and Asynchronous Signals The MPC5200B contains several sets if I/Os that do not require special setup, hold, or valid requirements. Most of these are asynchronous to the system clock.
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tCK tDH tDV Output valid tIH tIS Input valid Figure 45. Timing Diagram—Asynchronous Signals MPC5200B Data Sheet, Rev.
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1.3.18 IEEE 1149.1 (JTAG) AC Specifications Table 51. JTAG Timing Specification Sym Characteristic Min Max Unit SpecID — TCK frequency of operation. 0 25 MHz A17.1 1 TCK cycle time. 40 — ns A17.2 2 TCK clock pulse width measured at 1.5V. 1.08 — ns A17.3 3 TCK rise and fall times. 0 3 ns A17.4 (1) 4 TRST setup time to tck falling edge . 10 — ns A17.5 5 TRST assert time. 5 — ns A17.6 5 — ns A17.7 15 — ns A17.8 0 30 ns A17.9 0 30 ns A17.
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TCK 6 7 INPUT DATA VALID DATA INPUTS 8 OUTPUT DATA VALID DATA OUTPUTS 9 DATA OUTPUTS Numbers shown reference Table 51. Figure 48. Timing Diagram—JTAG Boundary Scan TCK 10 11 INPUT DATA VALID TDI, TMS 12 OUTPUT DATA VALID TDO 13 TDO Numbers shown reference Table 51. Figure 49. Timing Diagram—Test Access Port 2 Package Description 2.1 Package Parameters The MPC5200B uses a 27 mm x 27 mm TE-PBGA package.
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2.2 Mechanical Dimensions Figure 50 provides the mechanical dimensions, top surface, side profile, and pinout for the MPC5200B, 272 TE-PBGA package. PIN A1 INDEX D C 0.2 4X A 272X 0.2 A E 0.35 A E2 D2 0.2 M NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER PARALLEL TO PRIMARY DATUM A. 4. PRIMARY DATUM A AND THE SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.
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2.3 Pinout Listings See details in the MPC5200B User’s Manual (MPC5200BUM). Table 52.
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Table 52.
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Table 52.
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Table 52.
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Table 52.
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Table 52. MPC5200B Pinout Listing (continued) Name 1 Alias Type VDD_MEM_IO — VDD_CORE — VSS_IO/CORE — SYS_PLL_AVDD — CORE_PLL_AVDD — Power Supply Output Driver Type Input Type Pull-up/ down All “open drain” outputs of the MPC5200B are actually regular three-state output drivers with the output data tied low and the output enable controlled.
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The relationship between VDD_IO_MEM and VDD_IO is non-critical during power-up and power-down sequences. VDD_IO_MEM (2.5 V or 3.3 V) and VDD_IO are specified relative to VDD_CORE. 3.1.1 Power Up Sequence If VDD_IO/VDD_IO_MEM are powered up with the VDD_CORE at 0 V, the sense circuits in the I/O pads cause all pad output drivers connected to the VDD_IO/VDD_IO_MEM to be in a high-impedance state. There is no limit to how long after VDD_IO/VDD_IO_MEM powers up before VDD_CORE must power up.
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3.3.2 Pull-up Requirements for the PCI Control Lines If the PCI interface is NOT used (and internally disabled) the PCI control pins must be terminated as indicated by the PCI Local Bus specification. This is also required for MOST/Graphics and Large Flash Mode. PCI control signals always require pull-up resistors on the motherboard (not the expansion board) to ensure that they contain stable values when no agent is actively driving the bus.
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Normally this interface is implemented, using a COP (common on-chip processor) connector. The COP allows a remote computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations of the MPC5200B. 3.4.2 e300 COP/BDM Interface There are two possibilities to connect the JTAG interface: using it with a COP connector and without a COP connector. 3.4.2.
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To reset the MPC5200B via the COP connector, the HRESET pin of the COP should be connected to the HRESET pin of the MPC5200B. The circuitry shown in Figure 54 allows the COP to assert HRESET or JTAG_TRST separately, while any other board sources can drive PORRESET.
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PORRESET PORRESET 10Kohm HRESET HRESET MPC5200B VDD 10Kohm SRESET VDD SRESET JTAG_TRST 10Kohm VDD JTAG_TMS 10Kohm VDD JTAG_TCK 10Kohm VDD JTAG_TDI TEST_SEL_0 JTAG_TDO Figure 55. JTAG_TRST Wiring for Boards without COP Connector 4 Ordering Information Table 54.
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5 Document Revision History Table 55 provides a revision history for this hardware specification. Table 55. Document Revision History Rev. No. Differences 1 Clock Frequencies table: 466 MHz was changed to 400 MHz for the e300 Processor Core 2 Added description for PCI CLK Slew Rate for PCI CLK Specifications table. Added description for minimum rates in the DDR SDRAM Memory Write Timing table. 3 Added one item to table “DDR SDRAM Memory Read Timing.” 4 Updated table “Ordering Information.
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MPC5200B Data Sheet, Rev.
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