Datasheet

System Design Information
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor 73
VDD_CORE/PLL_AVDD and VDD_IO/VDD_IO_MEM should track up to 0.9 V and then separate for
the completion of ramps with VDD_IO/VDD_IO_MEM going to the higher external voltages. One way
to accomplish this is to use a low drop-out voltage regulator.
5.1.2 Power Down Sequence
If VDD_CORE/PLL_AVDD are powered down first, then sense circuits in the I/O pads will cause all
output drivers to be in a high impedance state. There is no limit on how long after VDD_CORE and
PLL_AVDD power down before VDD_IO or VDD_IO_MEM must power down. VDD_CORE should not
lag VDD_IO, VDD_IO_MEM, or PLL_AVDD going low by more than 0.4V during power down or there
will be undesired high current in the ESD protection diodes. There are no requirements for the fall times
of the power supplies.
The recommended power down sequence is as follows:
Drop VDD_CORE/PLL_AVDD to 0V.
Drop VDD_IO/VDD_IO_MEM supplies.
5.2 System and CPU Core AVDD power supply filtering
Each of the independent PLL power supplies require filtering external to the device. The following
drawing is a recommendation for the required filter circuit.
Figure 53. Power Supply Filtering
5.3 Pull-up/Pull-down Resistor Requirements
The MPC5200 requires external pull-up or pull-down resistors on certain pins.
5.3.1 Pull-down Resistor Requirements for TEST pins
The MPC5200 requires pull-down resistors on the test pins TEST_MODE_0, TEST_MODE_1,
TEST_SEL_1.
AVDD device pinPower
Supply
source
< 1 Ω
10 Ω
200-400 pF
10 µF