Datasheet

MPC5200 Data Sheet, Rev. 4

System Design Information

Freescale Semiconductor72

Figure 52. Supply Voltage Sequencing

The relationship between VDD_IO_MEM and VDD_IO is non-critical during power-up and power-down

sequences. Both VDD_IO_MEM (2.5 V or 3.3 V) and VDD_IO are specified relative to VDD_CORE.

5.1.1 Power Up Sequence

If VDD_IO/VDD_IO_MEM are powered up with the VDD_CORE at 0V, the sense circuits in the I/O pads

will cause all pad output drivers connected to the VDD_IO/VDD_IO_MEM to be in a high-impedance

state. There is no limit to how long after VDD_IO/VDD_IO_MEM powers up before VDD_CORE must

power up. VDD_CORE should not lead the VDD_IO, VDD_IO_MEM or PLL_AVDD by more than 0.4

V during power ramp up or there will be high current in the internal ESD protection diodes. The rise times

on the power supplies should be slower than 1 microsecond to avoid turning on the internal ESD protection

clamp diodes.

The recommended power up sequence is as follows:

Use one microsecond or slower rise time for all supplies.

1.5V

2.5V

3.3V

DC Power Supply Voltage

VDD_IO,

VDD_IO_MEM (SDR)

VDD_IO_MEM (DDR)

VDD_CORE,

PLL_AVDD

Note:

1. VDD_CORE should not exceed VDD_IO, VDD_IO_MEM or PLL_AVDD by more than

0.4 V at any time, including power-up.

2. It is recommended that VDD_CORE/PLL_AVDD should track VDD_IO/VDD_IO_MEM

up to 0.9 V then separate for completion of ramps.

3. Input voltage must not be greater than the supply voltage (VDD_IO, VDD_IO_MEM,

VDD_CORE, or PLL_AVDD) by more than 0.5 V at any time, including during power-up.

4. Use 1 microsecond or slower rise time for all supplies.

Time