Datasheet

MPC5200 Data Sheet, Rev. 4
Electrical and Thermal Characteristics
Freescale Semiconductor54
Figure 38. Timing Diagram — 8,16, 24, and 32-bit CODEC / I
2
S Master Mode
NOTE
Output timing was specified at a nominal 50 pF load.
Table 43. Timing Specifications — 8,16, 24, and 32-bit CODEC / I
2
S Slave Mode
Sym Description Min Typ Max Units SpecID
1 Bit Clock cycle time 40.0 — — ns A15.9
2 Clock pulse width — 50 — %
1
NOTES:
1
Bit Clock cycle time
A15.10
3 FrameSync setup time 1.0 — — ns A15.11
4 Output Data valid after clock edge — — 14.0 ns A15.12
5 Input Data setup time 1.0 — — ns A15.13
6 Input Data hold time 1.0 — — ns A15.14
BitClk
5
3
4
3
4
(CLKPOL=0)
BitClk
(CLKPOL=1)
Frame
(SyncPol = 1)
TxD
Output
Output
Output
6
7
8
Output
Frame
(SyncPol = 0)
Output
RxD
Input
1
22