Datasheet

Electrical and Thermal Characteristics
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor 53
3.3.15 PSC
3.3.15.1 Codec Mode (8,16,24 and 32-bit) / I
2
S Mode
NOTE
Output timing was specified at a nominal 50 pF load.
Table 42. Timing Specifications—8,16, 24 and 32-bit CODEC / I
2
S Master Mode
Sym Description Min Typ Max Units SpecID
1 Bit Clock cycle time, programmed in CCS register 40.0 — — ns A15.1
2 Clock pulse width — 50 — %
1
NOTES:
1
Bit Clock cycle time
A15.2
3 Bit Clock fall time — — 7.9 ns A15.3
4 Bit Clock rise time — — 7.9 ns A15.4
5 FrameSync valid after clock edge — — 8.4 ns A15.5
6 FrameSync invalid after clock edge — — 8.4 ns A15.6
7 Output Data valid after clock edge — — 9.3 ns A15.7
8 Input Data setup time 6.0 — — ns A15.8