Datasheet

Electrical and Thermal Characteristics
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor 45
Figure 29. Ethernet Timing Diagram—MII Tx Signal
Figure 30. Ethernet Timing Diagram—MII Async
Table 32. MII Tx Signal Timing
Sym Description Min Max Unit SpecID
M5 TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER
Delay
025 ns A9.5
M6 TX_CLK pulse width high 35% 65% TX_CLK Period
1
NOTES:
1
the TX_CLK frequency shall be 25% of the nominal transmit frequency, e.g., a PHY operating at 100 Mb/s must
provide a TX_CLK frequency of 25 MHz and a PHY operating at 10 Mb/s must provide a TX_CLK frequency of 2.5
MHz. See the IEEE 802.3 Specification [6].
A9.6
M7 TX_CLK pulse width low 35% 65% TX_CLK Period
(1)
A9.7
Table 33. MII Async Signal Timing
Sym Description Min Max Unit SpecID
M8 CRS, COL minimum pulse width 1.5 — TX_CLK Period A9.8
M7
M6
M5
TX_CLK (Input)
TXD[3:0] (Outputs)
TX_EN
TX_ER
M8
CRS, COL