Datasheet

MPC5200 Data Sheet, Rev. 4
Electrical and Thermal Characteristics
Freescale Semiconductor36
Figure 16. Multiword DMA Timing
Table 29. Ultra DMA Timing Specification
Name
MODE 0
(ns)
MODE 1
(ns)
MODE 2
(ns)
Comment SpecID
Min Max Min Max Min Max
(t)
2CYC
240 — 160 — 120 — Typical sustained average two cycle time.
For information only, do not test.
A8.26
(t)
CYC
114 — 75 — 55 — Cycle time allowing for asymmetry and clock
variations from STROBE edge to STROBE edge
A8.27
(t)
2CYC
235 — 156 — 117 — Two-cycle time allowing for clock variations, from
rising edge to next rising edge or from falling edge to
next falling edge of STROBE.
A8.28
(t)
DS
15 — 10 — 7 — Data setup time at recipient. A8.29
(t)
DH
5—5—5—Data hold time at recipient. A8.30
(t)
DVS
70 — 48 — 34 — Data valid setup time at sender, to STROBE edge. A8.31
(t)
DVH
6 — 6 — 6 — Data valid hold time at sender, from STROBE edge. A8.32
(t)
FS
0 230 0 200 0 170 First STROBE time for drive to first negate DSTROBE
from STOP during a data-in burst.
A8.33
t0
tC
tE
tI tD
tF
tS
tH
tG
tJ
DMARQ
RDATA
WDATA
(Drive)
(Host)
(Host)
(Drive)
(Host)
tL
tK
NOTE: The directionof signalassertionis towardsthe
top of the page, and the direction of negation is
towards the bottom of the page, irrespective of the
electrical properties of the signal.
DMACK
DIOR
DIOW