Datasheet

MPC5200 Data Sheet, Rev. 4
Electrical and Thermal Characteristics
Freescale Semiconductor32
3.3.7.3 MUXed Mode
Note:
1. ACK can shorten the CS pulse width.
Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified 0 - 65535.
2. ACK is input and can be used to shorten the CS pulse width.
Table 26. MUXed Mode Timing
Sym Description Min Max Units Notes SpecID
t
CSA
PCI CLK to CS assertion - 1.8 ns A7.15
t
CSN
PCI CLK to CS negation - 1.8 ns A7.16
t
ALEA
PCI CLK to ALE assertion - 1 ns A7.16
t
1
ALE assertion before Address, Bank,
TSIZ assertion
- 0.8 ns A7.17
t
2
CS assertion before Address, Bank,
TSIZ negation
- 0.7 ns A7.18
t
3
CS assertion before Data wr valid - 0.7 ns A7.19
t
4
Data wr hold after CS negation t
IPBIck
- ns A7.20
t
5
Data rd setup before CS negation 2.8 - ns A7.21
t
6
Data rd hold after CS negation 0 (DC+1)*t
PCIck
ns 1 A7.22
t
7
ALE pulse width - t
PCIck
ns A7.23
t
TSA
CS assertion after TS assertion - 0.8 ns A7.24
t
8
TS pulse width - t
PCIck
ns A7.24
t
9
CS pulse width (2+WS)*t
PCIck
(2+WS)*t
PCIck
ns A7.25
t
OEA
OE assertion before CS assertion - 0.4 ns A7.26
t
OEN
OE negation before CS negation - 0.4 ns A7.27
t
10
RW assertion before ALE assertion t
IPBIck
- ns A7.26
t
11
RW negation after CS negation - t
PCIck
ns A7.27
t
12
ACK assertion after CS assertion t
IPBIck
-ns2A7.28
t
13
ACK negation after CS negation - t
PCIck
ns 2 A7.28