Datasheet

MPC5200 Data Sheet, Rev. 4
Electrical and Thermal Characteristics
Freescale Semiconductor30
3.3.7.2 Burst Mode
Table 25. Burst Mode Timing
NOTES:
1. Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified 0 - 65535.
2. Example:
Long Burst is used, this means the CS related BERx and SLB bits of the Chip Select Burst Control Register are set and a
burst on the internal XLB is executed. => LB = 1
Data bus width is 8 bit. => DS = 8
=> 4
1
*2*(32/8) = 32 => ACK is asserted for 32 PCI cycles to transfer one cache line.
Wait State is set to 10. => WS = 10
1+10+32 = 43 => CS is asserted for 43 PCI cycles.
3. ACK is output and indicates the burst.
Sym Description Min Max Units Notes SpecID
t
CSA
PCI CLK to CS assertion - 1.8 ns A7.20
t
CSN
PCI CLK to CS negation - 1.8 ns A7.21
t
1
CS pulse width (1+WS+4
LB
*2*(32/DS))*
t
PCIck
(1+WS+4
LB
*2*(32/DS))
*t
PCIck
ns 1,2 A7.22
t
2
ADDR valid before CS assertion t
IPBIck
t
PCIck
ns A7.23
t
3
ADDR hold after CS negation - -0.7 ns A7.24
t
4
OE assertion before CS assertion - 0.4 ns A7.25
t
5
OE negation before CS negation - 0.4 ns A7.26
t
6
RW valid before CS assertion t
PCIck
- ns A7.27
t
7
RW hold after CS negation t
PCIck
- ns A7.28
t
8
DATA setup before rising edge of
PCI
1.8 - ns A7.29
t
9
DATA hold after rising edge of PCI 0 - ns A7.30
t
10
DATA hold after CS negation 0 (DC+1)*t
PCIck
ns A7.31
t
11
ACK assertion after CS assertion - (WS+1)*t
PCIck
ns A7.32
t
12
ACK negation before CS negation - 0.6 ns 3 A7.33
t
13
ACK pulse width 4
LB
*2*(32/DS)*t
PCIck
4
LB
*2*(32/DS)*t
PCIck
ns 2,3 A7.34
t
14
CS assertion after TS assertion - 0.8 ns A7.35
t
15
TS pulse width t
PCIck
t
PCIck
ns A7.36