Datasheet

MPC5200 Data Sheet, Rev. 4
Electrical and Thermal Characteristics
Freescale Semiconductor28
3.3.7 Local Plus Bus
The Local Plus Bus is the external bus interface of the MPC5200. Maximum eight configurable
Chip-selects are provided. There are two main modes of operation: non-MUXed (Legacy and Burst) and
MUXED. The reference clock is the PCI CLK. The maximum bus frequency is 66 MHz.
Definition of Acronyms and Terms:
WS = Wait State
DC = Dead Cycle
LB = Long Burst
DS = Data size in Byte
tPCIck = PCI clock period
tIPBIck = IPBI clock period
Figure 11. Timing Diagram—IPBI and PCI clock (example ratio: 4:1)
3.3.7.1 Non-MUXed Mode
Table 24. Non-MUXed Mode Timing
Sym Description Min Max Units Notes SpecID
t
CSA
PCI CLK to CS assertion - 1.8 ns A7.1
t
CSN
PCI CLK to CS negation - 1.8 ns A7.2
t
1
CS pulse width (2+WS)*t
PCIck
(2+WS)*t
PCIck
ns 1 A7.3
t
2
ADDR valid before CS assertion t
IPBIck
t
PCIck
ns A7.4
t
3
ADDR hold after CS negation t
IPBIck
-ns2A7.5
t
4
OE assertion before CS assertion - 0.4 ns A7.6
t
5
OE negation before CS negation - 0.4 ns A7.7
t
6
RW valid before CS assertion t
PCIck
-nsA7.8
t
7
RW hold after CS negation t
IPBIck
-nsA7.9
t
8
DATA output valid before CS assertion t
IPBIck
- ns A7.10
t
9
DATA output hold after CS negation t
IPBIck
- ns A7.11
t
10
DATA input setup before CS negation 2.8 - ns A7.12
t
11
DATA input hold after CS negation 0 (DC+1)*t
PCIck
ns A7.13
t
12
ACK assertion after CS assertion t
PCIck
-ns3A7.14
t
13
ACK negation after CS negation - t
PCIck
ns 3 A7.15
PCI CLK
IPBI CLK
tIPBIck
tPCIck