Datasheet

MPC5200 Data Sheet, Rev. 4
Electrical and Thermal Characteristics
Freescale Semiconductor24
Figure 8. Read Data sample window depend on the number of Tap delay
The position of the t
data_valid
window is depend on the clock / data flight time on the board. The MDQS
signal indicate if the read data are valid. If the controller is not able to detect a valid MDQS signal on the
sample time (sample position A) then the controller will look for valid MDQS / data on the next edge of
the MEM_CLK signal (sample position B). Depend on the board travel time, different working tap delay
configurations are possible. For a fast connection the data will be sampled with the next edge of
MEM_CLK, this shows Figure 8, sample position A. With a longer connection maybe two sample
positions are possible. Figure 8 shows a example with two working sample position (A and B). With a
bigger board delay only sample position B will be possible.
The equation below shows how to calculate the upper and lower limit. The right Tap delay number is
selected, when the possible max and min sample timing is within the memory data valid window.
•t
data_sample_max
= max((1.55 + TapNum * 0.095), (1.74 + TapNum * 0.045))
•t
data_sample_min
= min((1.55 + TapNum * 0.095), (1.74 + TapNum * 0.045))
delay [ns]
31
0
1.55
4.59
Possible sample
time over PVT for one
Memory Data valid window
selected Tap delay
Tap delay number
8.34
Working Tap Delay range
for sample position A
Working Tap Delay range
for sample position B
t
data_valid_min
t
data_valid_max
t
data_sample_min
t
data_sample_min
selected Tap delay