Datasheet

Analog Integrated Circuit Device Data
Freescale Semiconductor 7
17C724
TIMING DIAGRAMS
TIMING DIAGRAMS
Figure 4. t
PLH
and t
PHL
Timing
Figure 5. Low-Voltage Detection Timing
Table 5. Truth Table
10%
50%
OUTA,
OUTB
90%
t
PLH
t
PHL
IN1,
IN2,
PSAVE
t
V
DD
DET
0%
V
DD
I
M
50%
t
V
DD
DET
1.0 V
2.5 V
V
DD
DETon
V
DD
DEToff
90%
(<1.0 µA)
INPUT OUTPUT
V
DD
DET
(20)
PSAVE
(19)
IN1A
IN2A
IN1B
IN2B
OUT1A
OUT2A
OUT1B
OUT2B
LLLLLEnabled
L H L H L Enabled
L L H L H Enabled
L H H Z Z Enabled
HXXZZDisabled
H : High
L : Low
Z : High impedance
X : Don’t care
Notes
19. Terminal 13 (PSAVE) is pulled up by an internal resistor.
20. When V
DD
is lower than V
DD
DET while V
M
is applied, output becomes “Z” (high impedance); however, when PSAVE = “H”, the
low-voltage shutdown detection circuit is disabled.