Datasheet

Revision History
B-2 Freescale Semiconductor
B.2 Changes Between Rev. 0.1 and Rev. 1
Figure 32-1 on
page 32-2
Changed “RAS0” and “RAS1” to “SDRAM_CS0” and “SDRAM_CS1.”
Table 32-1 on
page 32-4
Added Ta ble 3 2- 1.
Table 33-3 on
page 33-3
Changed max input high voltage to 5.25 V.
Appendix A,
“Register Memory
Map
Changed “System Integration Module” to “System Control Module.”
Table B-2. Rev. 0.1 to Rev. 1 Changes
Location Description
Figure 6-1 on page
6-3
Replaced Figure 6-1 with a more accurate block diagram.
6.2/6-2 Enhanced discussion of Flash blocks.
6.3.4.3/6-10 Added “Note:
Enabling Flash security will disable BDM communications.”
6.3.4.3/6-10 Added “Note: When Flash security is enabled, the chip will boot in single chip mode regardless
of the external reset configuration.”
6.4.3.1/6-17 Changed text in Step 1 to read “If f
SYS
÷ 2 is greater than 12.8 MHz, PRDIV8 = 1; otherwise PRDIV8 = 0.”
6.4.3.1/6-17 Changed equation in Step 2 to the following:
6.4.3.1/6-17 Changed equation in Step 3 to the following:
6.4.3.1/6-17 Changed equations in example to reflect revisions above.
6.4.3.1/6-17 Changed text to read “So, for f
SYS
= 66 MHz, writing 0x54 to CFMCLKD will set FCLK to 196.43 kHz which
is a valid frequency for the timing of program and erase functions.”
6.4.3.1/6-17 Changed text to read “Consider the follwoing example for f
SYS
= 66 MHz.”
Table 6-12 on page
6-16
Added “Page erase verify” category.
Table 6-13 on page
6-19
Added “Page erase verify” category and description.
Table 6-14 on page
6-23
Added “Access error” row.
Table B-1. Rev. 0 to Rev. 0.1 Changes (continued)
Location Description
f
SYS
2 x 200kHz x (1 + (PRDIV8 x 7))
DIV[5:0] =
f
SYS
2 x (DIV[5:0] + 1) x (1 + (PRDIV8 x 7))
f
CLK
=
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3