Datasheet

Debug Support
Freescale Semiconductor 30-3
branch target address calculation is based on the contents of a program-visible register (variant
addressing). DDATA outputs can be configured to display the target address of such instructions in
sequential nibble increments across multiple processor clock cycles, as described in Section 30.3.1,
“Begin Execution of Taken Branch (PST = 0x5).” Two 32-bit storage elements form a FIFO buffer
connecting the processor’s high-speed local bus to the external development system through PST[3:0] and
DDATA[3:0]. The buffer captures branch target addresses and certain data values for eventual display on
the DDATA port, one nibble at a time starting with the least significant bit (lsb).
Execution speed is affected only when both storage elements contain valid data to be dumped to the
DDATA port. The core stalls until one FIFO entry is available.
Table 30-2 shows the encoding of these signals.
Table 30-2. Processor Status Encoding
PST[3:0]
Definition
Hex Binary
0x0 0000 Continue execution. Many instructions execute in one processor cycle. If an instruction requires more
processor clock cycles, subsequent clock cycles are indicated by driving PST outputs with this encoding.
0x1 0001 Begin execution of one instruction. For most instructions, this encoding signals the first processor clock
cycle of an instruction’s execution. Certain change-of-flow opcodes, plus the PULSE and WDDATA
instructions, generate different encodings.
0x2 0010 Reserved
0x3 0011 Entry into user-mode. Signaled after execution of the instruction that caused the ColdFire processor to
enter user mode.
0x4 0100 Begin execution of PULSE and WDDATA instructions. PULSE defines logic analyzer triggers for debug
and/or performance analysis. WDDATA lets the core write any operand (byte, word, or longword) directly
to the DDATA port, independent of debug module configuration. When WDDATA is executed, a value of
0x4 is signaled on the PST port, followed by the appropriate marker, and then the data transfer on the
DDATA port. Transfer length depends on the WDDATA operand size.
0x5 0101 Begin execution of taken branch. For some opcodes, a branch target address may be displayed on
DDATA depending on the CSR settings. CSR also controls the number of address bytes displayed,
indicated by the PST marker value preceding the DDATA nibble that begins the data output. See
Section 30.3.1, “Begin Execution of Taken Branch (PST = 0x5).”
0x6 0110 Reserved
0x7 0111 Begin execution of return from exception (RTE) instruction.
0x8–
0xB
1000–
1011
Indicates the number of bytes to be displayed on the DDATA port on subsequent processor clock cycles.
The value is driven onto the PST port one CLKOUT cycle before the data is displayed on DDATA.
0x8 Begin 1-byte transfer on DDATA.
0x9 Begin 2-byte transfer on DDATA.
0xA Begin 3-byte transfer on DDATA.
0xB Begin 4-byte transfer on DDATA.
0xC 1100 Exception processing. Exceptions that enter emulation mode (debug interrupt or optionally trace)
generate a different encoding, as described below. Because the 0xC encoding defines a multiple-cycle
mode, PST outputs are driven with 0xC until exception processing completes.
0xD 1101 Entry into emulator mode.
Displayed during emulation mode (debug interrupt or optionally trace).
Because this encoding defines a multiple-cycle mode, PST outputs are driven with 0xD until exception
processing completes.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3