Datasheet

Reset Controller Module
Freescale Semiconductor 29-9
29.5.2.1 Synchronous Reset Requests
In this discussion, the reference in parentheses refer to the state numbers in Figure 29-4. All cycle counts
given are approximate.
If the external RSTI
signal is asserted by an external device for at least four rising CLKOUT edges (3), if
the watchdog timer times out, or if software requests a reset, the reset control logic latches the reset request
internally and enables the bus monitor (5). When the current bus cycle is completed (6), RSTO
is asserted
(7). The reset control logic waits until the RSTI signal is negated (8) and for the PLL to attain lock (9, 9A)
before waiting 512 CLKOUT cycles (1). The reset control logic may latch the configuration according to
the RCON signal level (11, 11A) before negating RSTO (12).
If the external RSTI signal is asserted by an external device for at least four rising CLKOUT edges during
the 512 count (10) or during the wait for PLL lock (9A), the reset flow switches to (8) and waits for the
RSTI signal to be negated before continuing.
29.5.2.2 Internal Reset Request
If reset is asserted by an asynchronous internal reset source, such as loss of clock (1) or loss of lock (2),
the reset control logic asserts RSTO (4). The reset control logic waits for the PLL to attain lock (9, 9A)
before waiting 512 CLKOUT cycles (1). Then the reset control logic may latch the configuration
according to the RCON pin level (11, 11A) before negating RSTO (12).
If loss of lock occurs during the 512 count (10), the reset flow switches to (9A) and waits for the PLL to
lock before continuing.
29.5.2.3 Power-On Reset/Low-Voltage Detect Reset
When the reset sequence is initiated by power-on reset (0), the same reset sequence is followed as for the
other asynchronous reset sources.
29.5.3 Concurrent Resets
This section describes the concurrent resets. As in the previous discussion references in parentheses refer
to the state numbers in Figure 29-4.
29.5.3.1 Reset Flow
If a power-on reset or low-voltage detect condition is detected during any reset sequence, the reset
sequence starts immediately (0).
If the external RSTI
pin is asserted for at least four rising CLKOUT edges while waiting for PLL lock or
the 512 cycles, the external reset is recognized. Reset processing switches to wait for the external RSTI
pin to negate (8).
If a loss-of-clock or loss-of-lock condition is detected while waiting for the current bus cycle to complete
(5, 6) for an external reset request, the cycle is terminated. The reset status bits are latched (7) and reset
processing waits for the external RSTI pin to negate (8).
If a loss-of-clock or loss-of-lock condition is detected during the 512 cycle wait, the reset sequence
continues after a PLL lock (9, 9A).
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3