Datasheet

Queued Analog-to-Digital Converter (QADC)
28-52 Freescale Semiconductor
trigger events. Because both queues may be triggered by the periodic/interval timer, see Section 28.8.9,
“Periodic/Interval Timer for a summary of periodic/interval timer reset conditions.
28.8.8 QADC Clock (QCLK) Generation
Figure 28-42 is a block diagram of the QCLK subsystem. The QCLK provides the timing for the A/D
converter state machine which controls the timing of the conversion. The QCLK is also the input to a
17-stage binary divider which implements the periodic/interval timer. To retain the specified analog
conversion accuracy, the QCLK frequency (f
QCLK
) must be within the tolerance specified in Chapter 33,
“Electrical Characteristics”.
Before using the QADC, the prescaler must be initialized with values that put the QCLK within the
specified range. Though most applications initialize the prescaler once and do not change it, write
operations to the prescaler fields are permitted.
Figure 28-42. QADC Clock Subsystem Functions
CAUTION
A change in the prescaler value while a conversion is in progress is likely to
corrupt the result. Therefore, any prescaler write operation should be done
only when both queues are in the disabled modes.
To accommodate the wide range of the system clock frequency, QCLK is generated by a programmable
prescaler which divides the system clock. To allow the A/D conversion time to be maximized across the
spectrum of system clock frequencies, the QADC prescaler permits the QCLK frequency to be software
selectable. The frequency of QCLK is set with the QPR field in QACR0.
28.8.9 Periodic/Interval Timer
The QADC periodic/interval timer can be used to generate trigger events at a programmable interval,
initiating execution of queue 1 and/or queue 2. The periodic/interval timer stays reset under these
conditions:
ATD Converter
State Machine
2
7
2
8
2
9
2
10
2
11
2
12
2
13
2
14
2
15
2
16
2
17
Periodic Timer/Interval Timer
Select
Binary Counter
Queue 1 and Queue 2 Timer
Mode Rate Selection
Input Sample Time
from CCW
SAR
SAR Control
Periodic/Interval Trigger
Event for Q1 and Q2
Prescaler
System Clock
2
8
10
2
QPR[6:0]
Divide
by 2
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3