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ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller MAPBGA 256 32-Bit 80 MHz I/O number 150
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Table Of Contents
Queued Analog-to-Digital Converter (QADC)
28-38 Freescale Semiconductor
The first three examples in Figure 28-23 through Figure 28-25 (S1, S2, and S3) show what happens when
a new trigger event is recognized before the queue has completed servicing the previous trigger event on
the same queue.
In situation S1 (Figure 28-23), one trigger event is being recognized on each queue while that queue is still
working on the previously recognized trigger event. The trigger overrun error status bit is set, and the
premature trigger event is otherwise ignored. A trigger event that occurs before the servicing of the
previous trigger event is through does not disturb the queue execution in progress.
Figure 28-23. CCW Priority Situation 1
In situation S2 (Figure 28-24), more than one trigger event is recognized before servicing of a previous
trigger event is complete. The trigger overrun bit is again set, but the additional trigger events are otherwise
ignored. After the queue is complete, the first newly detected trigger event causes queue execution to begin
again. When the trigger event rate is high, a new trigger event can be seen very soon after completion of
the previous queue, leaving little time to retrieve the previous results. Also, when trigger events are
occurring at a high rate for queue 1, the lower priority queue 2 channels may not get serviced at all.
Figure 28-24. CCW Priority Situation 2
Situation S3 (Figure 28-25) shows that when the pause feature is used, the trigger overrun error status bit
is set the same way and that queue execution continues unchanged.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3