Datasheet

Queued Analog-to-Digital Converter (QADC)
Freescale Semiconductor 28-29
Specifically, this means that while the QADC is operating, the data in the result registers can change from
one read to the next. Simply initiating a read of one result register will not prevent another from being
updated with a new conversion result.
Thus, to read any given number of result registers coherently, the queue or queues capable of modifying
these registers must be inactive. This can be guaranteed by system operating conditions (such as, known
completion of a software-initiated queue single-scan or no possibility of an externally triggered/gated
queue scan) or by simply disabling the queues (writing MQ1 and/or MQ2 to 0).
28.7.2 External Multiplexing
External multiplexer chips concentrate a number of analog signals onto a few QADC inputs. This is useful
for applications that need to convert more analog signals than the QADC converter can normally support.
External multiplexing also puts the multiplexed chip closer to the signal source. This minimizes the
number of analog signals that need to be shielded due to the proximity of noisy high speed digital signals
at the microcontroller chip.
For example, four 4-input multiplexer chips can be put at the connector where the analog signals first
arrive on the printed circuit board. As a result, only four analog signals need to be shielded from noise as
they approach the microcontroller chip, rather than having to protect 16 analog signals. However, external
multiplexer chips may introduce additional noise and errors if not properly utilized. Therefore, it is
necessary to maintain low “on” resistance (the impedance of an analog switch when active within a
multiplexed chip) and insert a low pass filter (R/C) on the input side of the multiplexed chip.
28.7.2.1 External Multiplexing Operation
The QADC can use from one to four external multiplexer chips to expand the number of analog signals
that may be converted. Up to 16 analog channels can be converted through external multiplexer selection.
The externally multiplexed channels are automatically selected from the channel field of the CCW, the
same as internally multiplexed channels. The QADC is configured for the externally multiplexed mode by
setting the MUX bit in control register 0 (QACR0).
Figure 28-18 shows the maximum configuration of four external multiplexer chips connected to the
QADC. The external multiplexer chips select one of four analog inputs and connect it to one analog output,
which becomes an input to the QADC. The QADC provides two multiplexed address signals, MA[1:0], to
select one of four inputs. These inputs are connected to all four external multiplexer chips. The analog
output of the four multiplexer chips are each connected to separate QADC inputs (ANW, ANX, ANY, and
ANZ) as shown in Figure 28-18
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3