Datasheet

Queued Analog-to-Digital Converter (QADC)
28-28 Freescale Semiconductor
28.6.8.3 Left-Justified Unsigned Result Register (LJURR)
28.7 Functional Description
This subsection provides a functional description of the QADC.
28.7.1 Result Coherency
The QADC supports byte and half-word reads and writes across a 16-bit data bus interface. All conversion
results are stored in half-word registers, and the QADC does not allow more than one result register to be
read at a time. For this reason, the QADC does not guarantee read coherency.
Table 28-19. LJSRR Field Descriptions
Bit(s) Name Description
15 S The left justified, signed format corresponds to a half-scale, offset binary, two’s
complement data format. Conversion values corresponding to 1/2 full scale, 0x0200,
or higher are interpreted as positive values and have a sign bit of 0. An unsigned, right
justified conversion of 0x0200 would be represented as 0x0000 in this signed register,
where the sign = 0 and the result = 0. For an unsigned, right justified conversion of
0x3FF (full range or V
RH
), the signed equivalent in this register would be 0x7FC0, sign
= 0 and result = 0x1FF. For an unsigned, right justified conversion of 0x0000 (V
RL
), the
signed equivalent in this register would be 0x8000, sign = 1 and result = 0x000, a two’s
complement value representing –512.
14–6 RESULT The conversion result is signed, left-justified data.
5–0 — Reserved, should be cleared.
15 8
Field RESULT
Reset Undefined
R/W: R/W
765 0
Field RESULT —
Reset Undefined
R/W: R/W R
Address IPSBAR + 0x19_0380, 0x19_03fe
Figure 28-17. Left-Justified Unsigned Result Register (LJURR)
Table 28-20. LJURR Field Descriptions
Bit(s) Name Description
15–6 RESULT The conversion result is unsigned, left-justified data.
5–0 — Reserved, should be cleared.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3