Datasheet

ColdFire Core
Freescale Semiconductor 2-9
2.3 Functional Description
2.3.1 Version 2 ColdFire Microarchitecture
From the block diagram in Figure 2-1, the non-Harvard architecture of the processor is readily apparent.
The processor interfaces to the local memory subsystem via a single 32-bit address and two unidirectional
32-bit data buses. This structure minimizes the core size without compromising performance to a large
degree.
A more detailed view of the hardware structure within the two pipelines is presented in Figure 2-9 and
Figure 2-10 below. In these diagrams, the internal structure of the instruction fetch and operand execution
pipelines is shown:
Figure 2-9. Version 2 ColdFire Processor Instruction Fetch Pipeline Diagram
IAG IC IB
Core Bus
Address
Core Bus
Read Data
Opword
Extension 1
Extension 2
FIFO
IB
+4
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3