Datasheet

Chip Configuration Module (CCM)
27-8 Freescale Semiconductor
27.6.2 Chip Mode Selection
The chip mode is selected during reset and reflected in the MODE field of the chip configuration register
(CCR). See Section 27.5.3.1, “Chip Configuration Register (CCR).” Once reset is exited, the operating
mode cannot be changed. Table 27-9 shows the mode selection during reset configuration.
CS0 RCON[4:3] = 00
RCON2 = 0
D[19:18] Boot Device
00 Internal with 32-bit port
5
10 External with 8-bit port
01 External with 16-bit port
11 External with 32-bit port
All output pins RCON5 = 1
D21 Output Pad Drive Strength
0 Partial strength
1 Full strength
5
Clock mode N/A
CLKMOD1, CLKMOD0 Clock Mode
00 External clock mode (PLL disabled)
01 1:1 PLL mode
10 Normal PLL mode with external
clock reference
11 Normal PLL mode w/crystal reference
A[23:21]/CS[6:4]
RCON[9:8] = 00
D[25:24] Chip Select Configuration
00 PF[7:5] = A[23:21]
5
10 PF[7] = CS6 / PF[6:5] = A[22:21]
01 PF[7:6] = CS6, CS5 / PF[5] = A[21]
11 PF[7:6] = CS6, CS5, CS4
1
Modifying the default configurations is possible only if the external RCON pin is asserted.
2
The D[31:27, 23:22, 20, 15:0] pins do not affect reset configuration.
3
The external reset override circuitry drives the data bus pins with the override values while RSTO is asserted. It must stop
driving the data bus pins within one CLKOUT cycle after RSTO is negated. To prevent contention with the external reset
override circuitry, the reset override pins are forced to inputs during reset and do not become outputs until at least one
CLKOUT cycle after RSTO
is negated.
4
RCON[0] has higher priority than RCON[3:2]. When RCON[0] is configured to boot the chip in single chip mode, the part will
boot internally with a 32-bit port overriding any configuration set by RCON[3:2].
5
Default configuration
Table 27-8. Configuration During Reset
1
(continued)
Pin(s) Affected
Default
Configuration
Override Pins
in Reset
2,34
Function
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3