Datasheet

ColdFire Core
Freescale Semiconductor 2-7
2.2.5 Program Counter (PC)
The PC contains the currently executing instruction address. During instruction execution and exception
processing, the processor automatically increments contents of the PC or places a new value in the PC, as
appropriate. The PC is a base address for PC-relative operand addressing.
The PC is initially loaded during reset exception processing with the contents of location 0x0000_0004.
2.2.6 Cache Control Register (CACR)
The CACR controls operation of the instruction/data cache memories. It includes bits for enabling,
freezing, and invalidating cache contents. It also includes bits for defining the default cache mode and
write-protect fields. The CACR is described in Section 4.2.1, “Cache Control Register (CACR).”
2.2.7 Access Control Registers (ACRn)
The access control registers define attributes for user-defined memory regions. These attributes include the
definition of cache mode, write protect, and buffer write enables. The ACRs are described in Section 4.2.2,
“Access Control Registers (ACR0, ACR1).”
2.2.8 Vector Base Register (VBR)
The VBR contains the base address of the exception vector table in memory. To access the vector table,
the displacement of an exception vector is added to the value in VBR. The lower 20 bits of the VBR are
not implemented by ColdFire processors. They are assumed to be zero, forcing the table to be aligned on
a 1 MB boundary.
BDM: 0x80F (PC) Access: User read/write
BDM read/write
313029282726252423222120191817161514131211109876543210
R
Address
W
Reset––––––––––––––––––––––––––––––––
Figure 2-6. Program Counter Register (PC)
BDM: 0x801 (VBR) Access: Supervisor read/write
BDM read/write
313029282726252423222120191817161514131211109876543210
R
Base Address
0 0 0 0 0 000000000 000 0 00
W
Reset00000000000000000000000000000000
Figure 2-7. Vector Base Register (VBR)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3